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Browse Prior Art Database

CMOS OUTPUT WITH PECL LEVELS

IP.com Disclosure Number: IPCOM000008046D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-15
Document File: 5 page(s) / 155K

Publishing Venue

Motorola

Related People

Duncan McFarland: AUTHOR [+2]

Abstract

The need for lower cost and more integrated solutions is driving many functions on to the same integrated circuit. With CMOS's low cost and den- sity advantages over other technologies more spe- cialized functions need to be implemented in CMOS. One such function is a high speed output capable of 1 gigabit per second data rates. Many applications in networking and parallel computing require such speed. As new network protocols such as Fibre Channel and lGb/s Ethernet become a real- ity, CMOS implementations will be required for complete integration into low cost solutions.

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MOTOROLA Technical Developments

CMOS OUTPUT WITH PECL LEVELS

by Duncan McFarland and Peter Econompoulos

  The need for lower cost and more integrated solutions is driving many functions on to the same integrated circuit. With CMOS's low cost and den- sity advantages over other technologies more spe- cialized functions need to be implemented in CMOS. One such function is a high speed output capable of 1 gigabit per second data rates. Many applications in networking and parallel computing require such speed. As new network protocols such as Fibre Channel and lGb/s Ethernet become a real- ity, CMOS implementations will be required for complete integration into low cost solutions.

  The output buffer to be described is a top rail referenced buffer where both Vol and Voh can be specified base on device sizing. The input control signal is fully CMOS compatible and requires no translation. By using two identical buffers with complementary input signals a high speed differen- tial output buffer can be constructed which can drive 75 ohm coaxial cable at a 1 gigabit data rate. (See Figure 1.)

  The buffer operates by using two P channel transistors which drive a termination load. The size of Tl is determined such that when driving the ter- mination load, the output voltage becomes the Voh level. The size of T2 is determined such that when driving the termination load, the output voltage becomes the Vol level. Buffer I1 provides isolation from the CMOS logic gate driving the output stmc- hue and insures fast edge rates on internal nodes. Buffer 12 performs two functions, one to insure that the gate voltages of Tl and T2 are out of phase required to generating proper Voh and Vol levels. The other function is as a delay element that insures

that the sequencing of transistor Tl and T2 are such that fast output edge rates are achieved with mini- mal undershoot.

  Figures 2, 3 and 4 are the results of transient simulations of the buffer driven by a 5OOMhz clock. The plots demonstrate the effect of different delay time of buffer I2 on the output edge rates. Figure 2 shows the correct timing relationship with the out- put rise time being driven by a large Tl device to the Voh level. The output falling edge is determined by the termination resistance and the output capaci- tive load. The output voltage falls on an RC time constant from Voh to ground until the delayed turn- on of transistor T2 forces the output to the Vol level. Figure 3 shows the effect of a short delay through buffer 12. Note that the falling edge is determined by the same RC time constant, but instead of a volt- age change from Voh to ground it becomes Voh to Vol producing an unacceptable edge rate and requires too much time to reach the Vol level. Figure 4 shows the effect of a long delay through buffer...