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Method for Creating Abrupt Extension Profiles and Low Resistance Source Drain Contact Regions

IP.com Disclosure Number: IPCOM000008088D
Original Publication Date: 2002-May-16
Included in the Prior Art Database: 2002-May-16
Document File: 5 page(s) / 76K

Publishing Venue

Motorola

Related People

Michael J. Rendon: INVENTOR [+4]

Abstract

We propose a method for implementation of laser annealing to activate the extension and source/drain (S/D) regions of a MOSFET, which allows laterally abrupt junctions in the extension region, good contact resistance, and low diode leakage - a combination not possible in previously published integrations.

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Method for Creating Abrupt Extension Profiles and Low Resistance Source Drain Contact Regions

Michael J. Rendon, Eric J. Verret, William J. Taylor, David C. Sing

Abstract

We propose a method for implementation of laser annealing to activate the extension and source/drain (S/D) regions of a MOSFET, which allows laterally abrupt junctions in the extension region, good contact resistance, and low diode leakage - a combination not possible in previously published integrations.

Introduction

For the near future, two of the leading issues for good transistor performance are laterally abrupt junctions between extension and channel, and contact resistance between silicide and source/drain (S/D) region.  Conventional annealing allows dopant diffusion, which degrades abruptness, and incomplete activation, which leads to poor contact resistance.  Laser annealing provides an advantage over conventional annealing in both of these areas, since the melt/recrystallize allows very abrupt interfaces, and activation above solid solubility.  A drawback of laser annealing, however, is the diode leakage resulting from incomplete annealing of the damage resulting from the amorphization implant necessary for laser melting.  The common method for addressing this diode leakage is to add a final anneal, which diffuses the junctions past the damage region - but this simultaneously degrades the abruptness and activation advantages which laser gave in the first place.

In this paper we describe several implementations of laser annealing, and propose a better one.

Fig. 1 shows different laser annealing integration schemes used to create advanced CMOS extension and S/D regions. 

The first laser annealing scheme shown in Fig. 1-A proposed by Park [1] et al has the initial step following gate definition as the extension PAI, which is followed by spacer deposition, S/D pre-amorphisation implant  (PAI), S/D and extension doping, and laser annealing to diffuse and activate the dopants in the S/D and extension regions.  Silicidation is required after the laser anneal to provide a low resistance contact to the transistor electrodes.   

Advantages of this process include a highly doped and laterally abrupt extension and deep contact regions.  Overlap resistance (Rolap), extension resistance (Rext), S/D resistance (RSD),  and contact resistance (Rcont) are minimized by the laser annealing melt of the amorphous regions used to activate dopants beyond solid solubility limits.  Forming the extension and S/D regions with a single laser annealing melt reduces the need for a low energy extension implant which can be a time consuming process step.  A removable spacer S/D process is avoided in this scheme yielding a process flow that is the most efficient of the ones listed.

Disadvantages of this laser annealing process scheme include high diode leakage from the deep S/D regions caused by the end of range damage from either the PAI or dopant implants.  The laser anneal does not drive the deep junction beyon...