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Analog & Baseband Stackchip Arrangement with Redistribution Layer

IP.com Disclosure Number: IPCOM000008089D
Original Publication Date: 2002-May-16
Included in the Prior Art Database: 2002-May-16
Document File: 4 page(s) / 191K

Publishing Venue

Motorola

Related People

Addi Mistry: INVENTOR [+7]

Abstract

As wireless connectivity among portable electronic systems such as cell phones, headsets and Personal Device Assistants (PDA) becomes more pervasive, greater demands are placed on production of cost effective and small form factor packaging technologies for VLSI integrated circuits. To meet these requirements, many new three-dimensional (3-D) packaging technologies have been developed by stacking the dice and placing them on a substrate consisting of signal, ground, and power planes. This disclosure defines a novel 3-D package for Analog/RF and Baseband (BB) dice which uses a method and apparatus to maintain high receive/transmit signal integrity of a digital radio in a Chip Scale Package (CSP) configuration. This is accomplished by integrating a RF shield on the digital die with an extra layer of grounded metal. This metal the redistribution layer (RDL) can be designed for additional ground and power planes and interconnects signal traces. This redistribution layer enables minimization in the number of signal layers required on the substrates and eliminates costly-layered substrates.

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Analog & Baseband Stackchip Arrangement with Redistribution Layer

Addi Mistry, John Gehman, Daryl Wilde, Jim Kleffner, Ross Carlton,

David Wontor, David Dean

 
 
Summary

As wireless connectivity among portable electronic systems such as cell phones, headsets and Personal Device Assistants (PDA) becomes more pervasive, greater demands are placed on production of cost effective and small form factor packaging technologies for VLSI integrated circuits. To meet these requirements, many new three-dimensional (3-D) packaging technologies have been developed by stacking the dice and placing them on a substrate consisting of signal, ground, and power planes. This disclosure defines a novel 3-D package for Analog/RF and Baseband (BB) dice which uses a method and apparatus to maintain high receive/transmit signal integrity of a digital radio in a Chip Scale Package (CSP) configuration. This is accomplished by integrating a RF shield on the digital die with an extra layer of grounded metal. This metal – the redistribution layer (RDL) can be designed for additional ground and power planes and interconnects signal traces. This redistribution layer enables minimization in the number of  signal layers required on the substrates and eliminates  costly-layered substrates.

3-D Packaging Method

Three-dimensional packaging technologies are well established and documented where either bare memory and microprocessor controller dice or MCM’s are stacked along the z-axis, enabling considerable gain in compactness. This z-plane technology has an inherent advantage of providing much shorter interconnection length, thereby minimizing parasitic capacitance and also reducing system power consumption. However, if the normal stacking method is applied between a Digital and Analog die, the digital interference will decrease the sensitivity of a communication system if a sensitive circuit such as LNA or VCO of the Analog is close to a highly active digital circuit as seen in Figure 1.

Higher Receive and Transmit Signal Integrity

To maintain high receive transmit signal integrity the interference power from the digital circuit has to be obstructed by a metal shield which is on top of the digital die. This metal shield obstructs radiation reaching the LNA and VCO on an analog circuit. In order to accomplish this the metal shield is wire bonded to the ground. The thickness of the metal shield has to be three times the skin depth. For instance, in order to shield frequencies 1 GHz and above the copper or aluminum or Gold thickness has to be (skin depth 2.7 x 3) = 8.1 micron. The skin depth as a function of frequency for copper, aluminum, and gold is shown in Figure 2.

Proof Of Concept

As shown in Figure 3, a typical digital processor would radiate interference power of –60 dBm with the power spectrum extending up to 1 GHz. The estimated parasitic capacitance between the digital and an anlog die is 43 fF which is a reactance of 4 K ohm at 900 MHz. Then at the 50 Ohm input impedance of...