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HIGH-DENSITY PCB LAYOUT FOR ISOLATION OF ELECTRICALLY SENSITIVE TRACES

IP.com Disclosure Number: IPCOM000008111D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-20
Document File: 3 page(s) / 151K

Publishing Venue

Motorola

Related People

Daniel R. Sommers: AUTHOR [+2]

Abstract

Certain types of circuits (e.g. crystal oscillators, antennas, RF receivers, audio amplifiers, etc.) are extremely sensitive to the electrical and electro- mechanical disturbances generated by electrical systems that switch relatively large amounts of power at high frequencies (esp. digital systems). Another characteristic of these types of sensitive circuits is that they are also sensitive to parasitic coupling within their host environment (e.g. capaci- tive coupling to neighboring traces). The ever- increasing levels of system integration is driving more and more mutually hostile circuitry into close proximity. This invention is an easily implemented shielding (aka. isolation) method for sensitive cir- cuitry that has reduced parasitic effects on the circuitry which it shields.

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MOTOROLA Technical Developments

HIGH-DENSITY PCB LAYOUT FOR ISOLATION OF ELECTRICALLY SENSITIVE TRACES

by Daniel R. Sommers and Bob Uskali

1.0 MAIN CONCEPT AND MOTIVATION

  Certain types of circuits (e.g. crystal oscillators, antennas, RF receivers, audio amplifiers, etc.) are extremely sensitive to the electrical and electro- mechanical disturbances generated by electrical systems that switch relatively large amounts of power at high frequencies (esp. digital systems). Another characteristic of these types of sensitive circuits is that they are also sensitive to parasitic coupling within their host environment (e.g. capaci- tive coupling to neighboring traces). The ever- increasing levels of system integration is driving more and more mutually hostile circuitry into close proximity. This invention is an easily implemented shielding (aka. isolation) method for sensitive cir- cuitry that has reduced parasitic effects on the circuitry which it shields.

2.0 IMPLEMENTATION

  The implementation is to bury a cross-hatched plate on a layer under the sensitive circuitry rotated by an angle off of the orthogonal axes of the sensi- tive traces above it thus minimizing the field effects. The actual design of the plate as well as its effectivity are all factors to be considered in the implementation of this procedure:

1) the shape of the plate,
2) at which point(s) the plate is attached to

the shield potential (usually, but not necessarily, ground)
3) the size of the holes in the cross-hatch
4) the angle of rotation for the cross hatch (minimizing trace metal overlaying plate metal)

The main strengths in the implementation of this procedure are:

1) ease of implementation (e.g. can be automated in the CAD process);
2) no additional product cost burden;
3) Relief of PCB tollerance variations for sensitive circuits

3.0 POSSIBLE DESIGN EXAMPLES

  Note the trade-offs between sensitive trace routing to minimize trace length and the angle of rotation of the grid in the isolation plate (GND in this case).

  An obvious improvement to this invention would be to hand-route the grid in the isolation plate and thereby further minimize the capacitive coupling. However, hand-routing must be traded against the time it takes to customize a grid; a regu- lar pattern...