Browse Prior Art Database

FLEA: FANOUT AND LOAD ESTIMATOR APPLICATION

IP.com Disclosure Number: IPCOM000008113D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-20
Document File: 4 page(s) / 170K

Publishing Venue

Motorola

Related People

Jeff L. Freeman: AUTHOR

Abstract

Typically, logic synthesis of chips is done in a piecemeal approach, since the current technology uses too much computer resources for design bier- archies of 50,000 gates or more (logic synthesis takes days to complete). By breaking up a design hierarchy into smaller logic synthesis runs, the throughput is much more manageable. However, this requires the designer to supply time budget constraints as well as fanout and load information for signals going to and from the sub-design of the chip hierarchy. Tbis disclosure presents a tool that can address the fanout and load information requirement.

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m M-LA Technical Developments

FLEA: FANOUT AND LOAD ESTIMATOR APPLICATION

by Jeff L. Freeman

INTRODUCTION

  Typically, logic synthesis of chips is done in a piecemeal approach, since the current technology uses too much computer resources for design bier- archies of 50,000 gates or more (logic synthesis takes days to complete). By breaking up a design hierarchy into smaller logic synthesis runs, the throughput is much more manageable. However, this requires the designer to supply time budget constraints as well as fanout and load information for signals going to and from the sub-design of the chip hierarchy. Tbis disclosure presents a tool that can address the fanout and load information requirement.

DESCRIPTION

  FLEA is a Per1 script that generates the fanout and loads estimates of all module output ports of each design in chip hierarch. It is unique because it generates these estimates before any synthesis is even done.

  FLEA reads in the technology library(s) to get a list of standard cells or custom cells (CELL-LIST). FLEA reads in a hierarchy information file from one of our Motorola internal tools "Synhier." This

information file will be used to determine whether a fanout and load estimation constraint file will be created. FLEA then calls a very fast Verilog parser from Motorola ADT called "Verilog2edif' (This

tool is used in the ADT Met toolset). The parser reads in a, Verilog description of a design and maps it to a generic set of primitive cells, writing out an EDlF netlist in the process. FLEA calls another set of tools from our HPESD tools group called "Edif2n" and "SC? These tools read the EDIF from Verilog2edif and create a net connectivity file. This is where the FLEA application begins.

  FLEA reads in the net connectivity file for the tools just described. The format of the net connec- tivity file is as follows:

net~number net_connection[l]. .net_connection N where

net-number is an integer identifier for the net net-connection[i] is a hierarchical name of an item attached to the net. There are N number of these items.

The items have the format: design[l]@instance[l]/. . ./design[N]/ instance[N]/pin(diiection)
where design[i] is the name of the cell in the bierachy instance[i] is the name of the corresponding instance name in the design hierarchy pm is the name of the pin of the hierarchical item direction is '5" for input pin, "x" for bidirectional pm, and "0" for output pin

Figure. 1 shows the program flow of the FLEA tool.

June 1997

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Technical Developments

/Calculate Fanout foreach net 1

Fig. 1 FLEA Process Flow

  Based on the net connectivity information, FLEA counts the number of standard cells for a given net number. It does this by matching CELL-LIST described above with each net-con- nection item. This count is used in the determina- tion of the fanout number of each net-connection item. For net-connection items that are not part of CELL-LIST, th...