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Method for embedded 3GIO lane reduction

IP.com Disclosure Number: IPCOM000008122D
Publication Date: 2002-May-20
Document File: 2 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for embedded 3GIO lane reduction. Benefits include improved functionality.

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Method for embedded 3GIO lane reduction

Disclosed is a method for embedded 3GIO lane reduction. Benefits include improved functionality.

Background

              3GIO is a standard interface that is being developed as a possible replacement to the slower PCI/PCI-X interface. Built into the specification is the concept of lanes. Each data lane (or signal pair) provides a data channel of 2.5-Gb/sec frequency or approximately 200 MB/sec of data throughput. The specification includes configurations of 1X, 2X, 4X, 8X, 12X, 16X, 32X and so on. 

Description

               The disclosed method reduces the number of lanes in a 3GIO device based on auto-negotiation results and the availability of lanes. The method is capable of using the maximum number or a lesser number of lanes as is detected or configured in the system.

              For example, multiplexers switch the incoming byte-long data to build frames that are supported in the silicon design (see Figure 1). The underlying design is not dependant on the number of lanes and maximum throughput to operate. Because of this independence from required sustained throughput, the design could be used in the 8X mode (that it was designed for), or in 1X, 2X, or 4X modes.

              Each of the eight wire lanes is mapped to the bytes required to support 1X, 2X, 4X or 8X operation. Because the internal data path is 64 bits (8 bytes), this data width must be maintained regardless of which lane configuration is used. The lane mappings shown are:

§         Lane 0 maps to every byte for 1X, 2X, 4X, and 8X operation

§         Lane 1 maps...