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Method for chipset support for an IOAPIC hot plug in 3GIO

IP.com Disclosure Number: IPCOM000008123D
Publication Date: 2002-May-20
Document File: 3 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for chipset support for an input/output advanced programmable interrupt controller (IOAPIC) hot plug in 3GIO. Benefits include improved functionality.

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Method for chipset support for an IOAPIC hot plug in 3GIO

Disclosed is a method for chipset support for an input/output advanced programmable interrupt controller (IOAPIC) hot plug in 3GIO. Benefits include improved functionality.

Background

              IOAPICs are devices that convert the side-band wire (level-sensitive) interrupts in a conventional PCI system to in-band (edge-sensitive, MSI) interrupt messages to the CPU. In the future, when wire interrupts reach end-of-life and in-band interrupt messages become the standard, IOAPICs would not be required.

              Edge-triggered interrupts have the advantage of inherently not having any data coherency issues during interrupt delivery. Edge-triggered interrupts are posted write transactions and push the payload data (moving towards memory) that they cover to the front-side bus.

              IOAPICs are conventionally a chipset solution. That is, IOAPIC is only integrated as part of a chipset component that serves as the bridge between the core-logic chipset interconnect (HL) and the industry-standard PCI bus. System line interrupts are routed to the IOAPIC in the chipset component to be converted into edge-triggered interrupts to the front-side bus. System interrupt scaling is inherently achieved with this scheme because each PCI bus comes with a local IOAPIC.

              Conventionally, chipsets transparently pass IOAPIC special cycles from the front-side bus to the APICs integrated with the south component of the chipset.

Description

              The disclosed method provides support for IOAPIC and an IOAPIC  hot plug in a system outside of the chipset domain. The method supports legacy wire interrupts (like in PCI) in a system architecture based on an in-band bus, such as 3GIO.

              For IOAPICs to convert the level-sensitive interrupts into edge-triggered interrupts, end-of-interrupt (EOI) notification is required...