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Method For Fully-Digital Oversampling Clock And Data Recovery

IP.com Disclosure Number: IPCOM000008125D
Publication Date: 2002-May-20
Document File: 4 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a fully-digital oversampling clock and data recovery. Benefits include automatically-synthesizable digital logic.

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Method For Fully-Digital Oversampling Clock And Data Recovery

Disclosed is a method for a fully-digital oversampling clock and data recovery. Benefits include automatically-synthesizable digital logic.

Background

              Conventional clock and data recovery can be divided into two main categories:

1.      Using an analog phase-locked loop (PLL)

2.      Using digital oversampling with a synchronous delay line (SDL) or a delay-locked loop (DLL)

              The first technique is entirely analog and requires painstaking design in order to meet the tight requirements of clock and data recovery. Because of the difficulties in its implementation and manufacturing, this technique is much less favored than the second technique.

              The second technique, denoted a Tracking Manchester Decoder (TMD), has been used with excellent results in 10-Mb/s and 100-Mb/s Ethernet chips. Its implementation is straightforward, while its manufacturability is high and indistinguishable from conventional digital circuits.

              Implementing an SDL or DLL requires special design expertise for implementing circuitry in the form of a carefully laid-out data path with painstaking attention to the capacitive loading on each SDL/DLL tap.

              A reported implementation of the TMD [1] relies on a 32-tap SDL for sampling the input data. The SDL provides the equivalent of a 320-MHz sampling clock (see Figure 1).

General description

              The disclosed method, denoted here a Digital TMD (DTMD), performs the clock and data recovery function that is required for data transmission in which the data and clock are combined into a single signal. The clock and data recovery function first extracts (recovers) the clock that is embedded in the signal and uses the clock to sample the signal for recovering the data. The higher layers of the data communications system then process this data.

              The DTMD is implemented in 10-Mb/s Ethernet clock and data recovery, where it results in a greatly simplified implementation over previous implementations. Nonetheless, the principles of operation of the disclosed method are applicable to any data communication system in which the clock and data are combined together for transmission and is not restricted to 10-Mb/s Ethernet. However, the speed of the available logic used to implement the disclosed method must be high enough to accomplish oversam...