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Method to move data directly between SATA devices without requiring temporary data storage

IP.com Disclosure Number: IPCOM000008127D
Publication Date: 2002-May-20
Document File: 4 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to move data directly between serial advanced technology attachment (SATA) devices without requiring temporary data storage. Benefits include improved performance.

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Method to move data directly between SATA devices without requiring temporary data storage

Disclosed is a method to move data directly between serial advanced technology attachment (SATA) devices without requiring temporary data storage. Benefits include improved performance.

Background

              Conventionally, moving data from a SATA device to another SATA device requires an intermediate data store in memory.

Description

              The purpose of this disclosure is to propose the concept and method for moving data directly from one SATA device to a peer SATA device without requiring the data to be temporarily stored in memory (see Figure 1).

              A transfer of data from SATA port 0 to SATA port 1 proceeds as follows. Each port controls SATA device 0 and SATA device 1, respectively. Each SATA port contains a direct memory access (DMA) controller that is used for bus mastering reads or writes on the host bus (the PCI-X bus, for example). One method for moving the data is to program the DMA inside SATA 0 to push (write) the data into the buffer space of the SATA 1. Another method to perform the transfer is to program the DMA inside SATA 1 to pull (read) the data from the buffer space in SATA 0.

              Transferring data between two SATA ports, with one SATA port acting as a bus master and the other SATA port acting as the bus slave, requires that the DMA control mechanism for one of the ports be disabled. Consider a data transfer from device 0 to device 1. The DMA controller for port 0 pushes the data from its first in, first out (FIFO) register into the FIFO register of port 1, or the DMA for port 1 pulls the data into its FIFO register from the FIFO register of port 0. In either case, only one port’s DMA controller is active. Each port’s FIFO register in the SATA host controller is accessed using a memory address range allocated to it.

              A data transfer from SATA Device 0 to SATA Device 1 can be accomplished using the following methods:

§         Using the SATA port 0 internal DMA to push the data to the peer device

1.      The local processor disables the DMA controller for port 1 and provides port 1 FIFO control to the SATA port 0 bus master. The DMA controller for port 0 moves the data from device 0 to device 1.

2.      The local processor programs the taskfile registers for device 0 and writes the DMA read command to the command register. This results in a register–host to device Frame Information Structure (FIS) to device 0.

3.      The local processor programs the DMA control registers for device 0 but does not arm the DMA (does not set the start bit in the DMA command register). The descriptor table is set up so that data is moved to addresses that fall within the memory range allocated to device 1. The port 0 DMA is not armed until port 1 is enabled to transmit data to device 1. That is, when port 1 is enabled to transmit data to device 1 at reception of a DMA activate FIS command from device 1. This approach prevents the port 0 bus master from requesting bus ownership until the port 1 contr...