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Method for changing the context of a PCI functions address space via a control register

IP.com Disclosure Number: IPCOM000008128D
Publication Date: 2002-May-20
Document File: 4 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for changing the context of a Peripheral Component Interconnect (PCI) functions address space via a control register. Benefits include improved functionality.

This text was extracted from a Microsoft Word document.
This is the abbreviated version, containing approximately 40% of the total text.

Method for changing the context of a PCI function’s address space via a control register

Disclosed is a method for changing the context of a Peripheral Component Interconnect (PCI) function’s address space via a control register. Benefits include improved functionality.

Background

              PCI-X configuration header space is composed of standard and extended (device-specific) configuration space (see Figure 1). For a conventional four serial advanced technology attachment (SATA) port PCI-X solution, several registers are required for the control of each SATA port, in addition to the standard ATA registers. They consist of SATA-specific registers and registers for built-in self-test (BIST) control, among other functions.

              In IDE mode, little space is available in which to place the registers. The PCI/IDE specification utilizes five of the six DWORDs allocated for base address registers (BARs). The base address registers are located in the PCI function’s standard configuration header, and are numbered BAR0 through BAR5. In IDE, BAR0 and BAR1 are allocated for primary IDE channel command/control. BAR2 and BAR3 are allocated for secondary IDE channel command/control. BAR4 is allocated for bus master control. This leaves one DWORD, BAR5, for a base address register that can be used to access these new SATA registers.

              In a PCI-X solution, the control registers cannot be placed into memory space because the PCI-X specification requires that any base address register, excluding the EROM base address register, that requests memory space be 64-bit addressable. With only one 32-bit DWORD available for a BAR, the DWORD cannot be used to request memory space. This last DWORD may only be used to request I/O space.

              However, mapping the control registers into BAR5 I/O space is not an optimal solution. The maximum amount of space that can be requested with an I/O BAR is 256 bytes. The number of control registers required for the four SATA ports exceeds 256 bytes.

General description

              The disclosed method changes the context of a PCI function’s address space using a control register. The method also applies to a PCI function’s configuration, I/O, or memory address space, effectively providing the function more space in which to map control registers or any other device-specific functions.

 


Advantages

              The disclosed method provides advantages, including:

§         Improved functionality due to the capability to make any range in configuration, memory or I/O space context-switchable based on a control register

Detailed description

              The disclosed method enables a register to address more storage than is conventionally supported. For example, BAR5, which is able to address only up to 256 bytes, can address multiple sets of 256 byte regions.

              A control register in the PCI function’s extended configuration space acts as a selector for the context of BAR5. While the total additional control registers for all four SATA ports do not fit within a 256-byte region, the additional control regist...