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Method for a DFT technique to minimize the test application time of two pattern tests

IP.com Disclosure Number: IPCOM000008157D
Publication Date: 2002-May-22
Document File: 6 page(s) / 140K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a design for test (DFT) technique to minimize the test application time of two pattern tests. Benefits include lowered test cost, due to reduced application time and tester data volume, improved test environment and improved reliability.

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Method for a DFT technique to minimize the test application time of two pattern tests

Disclosed is a method for a design for test (DFT) technique to minimize the test application time of two pattern tests. Benefits include lowered test cost, due to reduced application time and tester data volume, improved test environment and improved reliability.

Background

              Some scan chains are made up of hold-scan cells. Such scan systems are comprised of two parts, the shadow register and the system register. Test data is shifted into the shadow register using the scan_shift operation. This test is applied to the system under test by transferring the data from the shadow register to the system register using the scan_store operation. The system response is captured using the system clock. Results from the system register are transferred to the shadow register using the scan_load operation. This result is then scanned out and the next test is scanned in.

              If transition testing is desired, pairs of vectors must be applied. For example, V1 and V2 are vector pairs. Rows 2-7, in column Load (see Figure 1), show the sequence of scan operations required to put the response into the shadow register. This operation must be followed by a scan_shift operation that scans out the response.

              Two scenarios occur under which transition tests can be computed. First, an independent set of vector pairs can be computed, such as (V1, V2), (V3, V4), (V5, V6). Each test requires two scan_shift operations before a response is in the shadow register. A second scenario assumes a sequence of tests, such as V1, V2, V3. The pairs (V1, V2), (V2, V3), (V3, V4) are the test pairs.

              The proposed scan modification is relevant to the second scenario. A test set that is generated using the first scenario includes test-pairs (V1, V2), (V3, V4), (V5,V6). Additional test pairs, such as (V2, V3), (V4, V5), enhance the total transition fault coverage.

              A major component of the total test application time of scan-based testing is the time taken to scan the test vectors. For transition tests, when hold scan is used, the situation is compounded in that for every test two test vectors must be scanned in.

Description

              This disclosed method includes a DFT technique that addresses the issue of test application time reduction for two pattern tests in a full-scan environment. The method assumes a hold-scan type of scan. Systems with hold scan in addition to the normal mode of operation provide the following scan operations during test mode: scan_load, scan_store and scan_shift. The disclosed method enhances the scan system by adding the scan_exchange operation during test mode.

              In this operation, the content of the shadow register is exchanged with the contents of the system register. Assume that initially the shadow register contains data S, and the system register con...