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Method for canceling cross-channel skew and controlling the read-delay of memory components

IP.com Disclosure Number: IPCOM000008163D
Publication Date: 2002-May-22
Document File: 5 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for canceling cross-channel skew and controlling the read-delay of memory components. The benefits include improved performance.

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Method for canceling cross-channel skew and controlling the read-delay of memory components

Disclosed is a method for canceling cross-channel skew and controlling the read-delay of memory components. The benefits include improved performance.

Background

              In a conventional high-speed memory subsystem with multiple memory devices in parallel, a command can arrive at the various memory devices at different times. As memory operating frequencies increase, the effects of skew become more severe. For example, in the case of a read, each parallel memory component device receives the read command at a different time. The read instruction can potentially drive data back on different clocks (depending on the amount of skew) and the frequency of the data clock/strobe.

              For example, the command is issued by the controller at time 0 (see Figure 1). The command is sent relative to a clock called CLK1. It arrives at the various memory devices at different times, T=t0 through T=tn. The data is returned relative to the data clock, CLK2, after a delay, D, after receiving the read command. Device 0 drives data back at t0+D. Device n drives back data at time tn+D, where tn is larger than t1. The controller receives data over a time period of tn-t0. This time-period is called cross-channel skew. The delay, D, at each memory component could vary based on the temperature, silicon speed, and voltage. The range of time over which data could arrive is long.

              Depending on the frequency of CLK2, the range could be larger than the period of CLK2. The cross-channel skew requires the controller to assemble data being received over multiple clocks and adds significant complexity of the controller design.

              Conventional acknowledgement signals are sent to signify the transfer of data on I/O buses, such as PCI or AGP. In these two bus interfaces, the IRDY# signal is used by the master to signify it is ready to transmit data.

General description

              The disclosed method is a device and apparatus to reduce or eliminate the cross-channel skew between parallel multiple memory component devices. The Flag signal is similar to the function of the conventional IRDY# signal. However, the Flag signal enables better control of read and write latency.

Key elements of the method include:

·        Flag signal can be generated by the issued read or write command, rather than the controller, and is sent out as a broadcast signal.

·        Flag signal is retimed to CLK2.

·        Flag signal is delayed by a timer or FIFO register, providing sufficient delay for memory components.

Advantages

              The disclosed method provides advantages, including:

·        Elimination of the signal pin on the controller

·        Improved memory controller flexibility and efficiency

·        Elimination of memory read latency

·        Simultaneous arrival of write data, regardless of cross-channel skew of the write command

Detailed description

              The disclosed method cancels cross-channel skew and controls the read delay of memory components. Sometime after the read command...