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IMPLEMENTATION OF A LOW-SKEW CLOCK DIVIDER CIRCUIT FOR LOW-POWER APPLICATIONS

IP.com Disclosure Number: IPCOM000008191D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-24
Document File: 1 page(s) / 55K

Publishing Venue

Motorola

Related People

Michael Torla: AUTHOR

Abstract

Traditional clock-divider circuits use a flip-flop following the path through the flip-flop, any skew and then a buffer to drive the output of the divider generated is simply associated with the tristate buffer. circuit. However, in wireless and other low-power applications, the clock-to-output delay on a flip-flop The figure below shows an example circuit. in the chosen library may result in clock skew Each flip-flop, with the inverting input, could between the source clock and the divided clock. constitute a clock divider circuit. Note that this This paper describes an alternative circuit to circuit includes an additional inverter and two generate a divided clock with much less skew. tristate buffers. The inverter that negates clock-in causes one flip-flop to operate exactly out-of-phase The theory behind this circuit is to use the input with the other. Thus, clka changes on the fall clock to enable a tristate buffer to drive an aheady- of clock-in, whereas clkb changes on the rise of setup value on the clock wire. Thus rather than skew clock-in.

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Technical Developments

IMPLEMENTATION OF A LOW-SKEW CLOCK DIVIDER CIRCUIT FOR LOW-POWER APPLICATIONS

by Michael Tot-la

  Traditional clock-divider circuits use a flip-flop following the path through the flip-flop, any skew and then a buffer to drive the output of the divider generated is simply associated with the tristate buffer. circuit. However, in wireless and other low-power
applications, the clock-to-output delay on a flip-flop The figure below shows an example circuit. in the chosen library may result in clock skew Each flip-flop, with the inverting input, could between the source clock and the divided clock. constitute a clock divider circuit. Note that this This paper describes an alternative circuit to circuit includes an additional inverter and two generate a divided clock with much less skew. tristate buffers. The inverter that negates clock-in causes one flip-flop to operate exactly out-of-phase The theory behind this circuit is to use the input with the other. Thus, clka changes on the fall clock to enable a tristate buffer to drive an aheady- of clock-in, whereas clkb changes on the rise of setup value on the clock wire. Thus rather than skew clock-in.

Example Low-Skew clock Divider Circuit

clock-out

  The tristate buffers are wired such that the many libraries, multiplexers with high drive buffer driving clka onto clock-out is enabled just are more expensive and slower than using the raw prior to the latching edge of the flip-flop generating...