Browse Prior Art Database

AN ARRAY BUS ARCHITECTURE FOR MEMORIES

IP.com Disclosure Number: IPCOM000008195D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-27
Document File: 4 page(s) / 182K

Publishing Venue

Motorola

Related People

John Dunn: AUTHOR [+3]

Abstract

A unique RAM implementation has been developed which uses an Array Bus architecture. In this structure one or more partitioned RAM blocks is controlled by a common Control Section. In the following the architecture, motivating factors, and implementation of the architecture will be discussed.

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Technical Developments

AN ARRAY BUS ARCHITECTURE FOR MEMORIES

by John Dunn, Theo Freund and Joseph Harris

INTRODUCTION

  A unique RAM implementation has been developed which uses an Array Bus architecture. In this structure one or more partitioned RAM blocks is controlled by a common Control Section. In the following the architecture, motivating factors, and implementation of the architecture will be discussed.

FEATURES OF ARCHITECTURE

made to meet customer specific requirements for a family of controllers to be built based on this architecture. The FASRAM module consists of a control section and multiple RAM array sections.

  Two primary issues drove the stmcture of the FASRAM: the need to provide a fast access port to the CPU while maintaining testability, and the need to place very large amounts of RAM on a chip while not conflicting with the modular methodology used on this family of microcontrollers. The FASRAM's Array Bus architecture with it's separate array and control sections meets these basic goals while offering increased functionality.

IMPLEMENTATION

  The Array Bus architecture isolates the actual RAM array of the FASRAM module from the Control Section. Each RAM Array block contains bit cells, row and column decoders, data drivers, as well as it's own sense amps. The Control Section has two primary functions: the Bus Interface to the system busses, and the interface to the array blocks. This latter function is carried out by muxing, control signal generation, and Array Bus drivers in the RAM Access (RA) block. Figure 1, "Example Implementation of the FASRAM" shows what a typical chip might look like. The physical separation of the control functionality from the RAM array has several advantages over current implementations used for memories in the modular design methodology. Also system functionality goals are more easily achieved as will be discussed.

l Modularity

Standard layout height modules are used in our methodology. Dimensions for the new array tit in this existing framework

l

Flexibility of configuration and orientation of RAM arrays on die

l

l Single Control Section

l Fast direct access from the CPU to the RAM

Access to control registers and RAM from primary system bus

Visibility Bus for viewing cycles on internal isolated bus connecting CPU and RAM

l

l

Comparators to facilitate code debug on micro- controller implementations without the Visibility Bus pinned out of the package

l Low Power design

MOTIVATION

The Fast Access Static RAM (FASRAM) architecture described here in reflects decisions

l

B Motoroh. Inc. ,997 123 June 1997

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MOTOROLA Technical Developments

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Control Section

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CPU

Fig. 1 Example Implementation of the FASRAM

  To meet desired goals of modularity and flexibility, the RAM array was split into multiple, identical blocks. Each block is of size 2K bytes accessible as 16 bit words. Existing RAM designs are set up to allow...