Browse Prior Art Database

CONCURRENT MULTI-LEVEL ARBITRATION

IP.com Disclosure Number: IPCOM000008196D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-27
Document File: 4 page(s) / 158K

Publishing Venue

Motorola

Related People

Yair Orbach: AUTHOR [+4]

Abstract

Arbitration is needed in every system having more than a single processor. Management of common resources (usually memory bus or commu- nication channel) can be centralized where "request" and "acknowledge" are sent to/from a supervisor, or can be managed in distributed form where arbitration logic is attached to each processor.

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M-LA Technical Developments

CONCURRENT MULTI-LEVEL ARBITRATION

by Yair Orbach, Heinrich losub, Effi Orian and Elchanan Rushinek

  Arbitration is needed in every system having more than a single processor. Management of common resources (usually memory bus or commu- nication channel) can be centralized where "request" and "acknowledge" are sent to/from a supervisor, or can be managed in distributed form where arbitration logic is attached to each processor.

  In both methods, a constant or variable priority is associated with each processor to decide if its request should be granted, based on parameters such as (i) its priority relative to other requesting proces- sors and (ii) the time that it has been waiting for the resource. Wait-time usually has an upper limit.

  Priority and wait-time limit can be in contention. When reaction time is important, as it usually is in real time systems, the wait-time limit can dominate and the system bus is toggled more often than is desired, decreasing bus efficiency. When bus efficiency is the primary concern, bus toggling can be reduced, but at the expense of longer wait-time. The impact of these choices can be large. For example, if bus toggling causes a loss of cycles when the bus cannot be used, and if fast response is also needed (e.g., ': 4 cycles delay to start servicing a processor or peripheral), then bus efficiency is - 49% at a 1 cycle loss and 33% at a 2 cycle loss.

   In Concurrent Multi-level Arbitration Priority (CMLAP) a relative arbitration priority is associated with each processor for normal activities. If the requesting processor has the highest relative priority, it will capture and hold the bus for a pre-defined period. When another processor indicates an urgent

(e.g., real time) request, the arbitrator promptly grants the bus to the demanding device for a short time sufficent for handling the urgent demand, such as interrupt response.

This CMLAP method allows the use of low

toggling rates for normal activities, thereby giving high bus efficiency, while also being able to provide rapid response for urgent tasks. The conflict between efficiency and response time is removed and the system can provide both, high efficiency bus throughput and fast response to interrupts. This is possible because in many practical cases urgent tasks like interrupts do not need the external bus for a long period but only for a few cycles. Thus their impact on bus throughput is small. Conversely, delaying an interrupt usually decreases system performance in the critical path.

  The invented arrangement applies to multi- processors with an arbitrator module which decides which processor will receive control of the bus, and to dual processors where control switches back and forth between the two processors. Block diagrams are provided. Figure 1 illustrates a multi-processor environment and Figure 2 a dual pr...