Browse Prior Art Database

QUANTUM SHIFT REGISTER

IP.com Disclosure Number: IPCOM000008210D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-28
Document File: 4 page(s) / 201K

Publishing Venue

Motorola

Related People

Jun Shen: AUTHOR

Abstract

A Shift Register circuit based on negative differential resistance (NDR) devices (e.g., resonant tunneling diodes, Esaki tunnel diodes, etc.) and transistors is proposed. The operation principle and circuit simulation results are provided.

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Technical Developments

QUANTUM SHIFT REGISTER

by Jun Shen

  A Shift Register circuit based on negative differential resistance (NDR) devices (e.g., resonant tunneling diodes, Esaki tunnel diodes, etc.) and transistors is proposed. The operation principle and circuit simulation results are provided.

  When two NDR diodes are connected in series and biased appropriately, the middle node is bi-stable. This bi-stable node can be controlled by connecting an input transistor to it. Figure 1 shows the equiva- lent circuit of the fundamental building block of the proposed Shift Register. It consists of two NDR diodes in series and an FET connected to the middle node. The diode on top (RTDl) has a peak current of about ZOmA and a valley current of 2mA. The diode on the bottom (RTD2) is 20% larger than RTDl to guarantee that RTDl switches to the valley first without input from the FET. The FET used in our simulation is an enhancement-mode FET and the threshold is zero. Figure 2 (a and b) shows the I-V characteristics of the diode and FET used in the simulations. During the operation, a constant drain voltage V14=0.65V is applied to node 14. When the gate V12=0, the FET is off. Sweeping Vll will produce the regular I-V characteristics of two RTD's in series (Figure 3a). Because RTDl is designed to be smaller than RTD2, RTDl will first switch to its valley at Vll-0.65V. The middle node V13 stays at logic low (<0.6X the peak voltage, Figure 3b). On the other hand, when the gate V12=0.65, the FET is turned on. A finite negative current (Ill- -1OmA) is flowing through the RTDl even when Vll=O. This current is equal to -l/2 of the drain current 114 of the FET (The other half flows through RTD2). As Vll increases, Ill increases. At a threshold Vll-0.35, the combined current Ill+114 exceeds the peak current of RTD2 and switch RTD2 to its valley state, setting V13 to its logic high (-0.65). This negative feedback (VU-

V13 -0, V14-V13 -0) turns off the FET (114 -0, Figure 2a).

  Repeating this building block by connecting the middle node 13 with the input gate of the next block forms the shift register. Figure 4 shows a two-stage shift register block. The two clock signals are 180- apart in phase (see simulation results in Figure 5). When the input is low and all the FET's are off, the RTDl's will be flipped to the valley state during each clock cycle, the middle nodes (13, 23, 33, and
43) are at logic low level. When the input is high, the FET is turned on. Extra driving current from the FET will pass throug...