Browse Prior Art Database

FULLY TESTABLE TRISTATE MULTIPLEXER FOR CIRCUITS WITH TIED DATA INPUTS

IP.com Disclosure Number: IPCOM000008215D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-28
Document File: 5 page(s) / 174K

Publishing Venue

Motorola

Related People

Mike Snyder: AUTHOR [+3]

Abstract

Multiplexers (mux) implemented using pass- gates are inherently challenging to test'. A weak pull-down device at the output (a.k.a. test pulldown) provides a test solution in a limited number of usage situations'. In this paper we describe a frequently occuring usage situation for pass-gate muxes-tied data inputs-for which the test pulldown solution fails to provide complete testability. We propose our invention-a pass-gate mux circuit-that is completely testable in the presence of tied data inputs. We show that the proposed circuit is better than alternate solutions in terms of area overhead, functional delay and design time overhead.

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@ M-LA

Technical Developments

FULLY TESTABLE TRISTATE MULTIPLEXER FOR CIRCUITS WITH TIED DATA INPUTS

by Mike Snyder, Rajesh Raina and Marvin Denman

1 INTRODUCTION

  Multiplexers (mux) implemented using pass- gates are inherently challenging to test'. A weak pull-down device at the output (a.k.a. test pulldown) provides a test solution in a limited number of usage situations'. In this paper we describe a frequently occuring usage situation for pass-gate muxes-tied data inputs-for which the test pulldown solution fails to provide complete testability. We propose our invention-a pass-gate mux circuit-that is completely testable in the presence of tied data inputs. We show that the proposed circuit is better than alternate solutions in terms of area overhead, functional delay and design time overhead.

2 THE TEST PROBLEM

Figure 1 shows an example of an untestable fault for an enable signal on a tristate driver which

has its data input tied. The figure shows three drivers A, B, C, driving onto the t&ate signal oat. In this case, a constant value of b'0' is driven onto the out signal if eO is b'l'; a constant value of b'l' is driven onto the out signal if el is b'l', and the value of the signal d2 is driven onto the oat signal if e2 is b'l'. It is assumed that only one signal of e0, el, and e2 is b'l' at any given time (i.e. one hot).

  In this example, it is assumed that the test vehicle has full control over the input signals e0, el, e2 and testgd_ers and full observability of the output signal our

  In this circuit it is impossible to detect stuck-at-O for the enable signal e0. Normally, to test for stuck-at- 0 for the enable signal e0, e0 would be forced b'l', and the other enables would be forced to b'0' while the weak test pulldown would be enabled to pull the tristate node low if it is left undriven. Since the data input to driver A is b'0' (stuck-at-O), and the

e0 (good part = b'l', bad part stuck-at-O)

-at-O
e. out (good part=b'O', bad

Enable eO stuc

IS not detectab 1

part = b'0')

Fig. 1 Example of untestable enable 'e0' signal

B Motorola Inc. ,997 June I997

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Technical Developments

test pulldown will pull out to b'O', it is impossible to a weak test pullup transistor and a new testgu-en-

detect if driver A is actually driving or not. (active low) signal has been added. tesrgu-en- and testqd-en can be independently controlled. In 3 SOLVING THE PROBLEM-THE INVENTION this case, out will be seen as b'0' for the good part and b' 1' for the bad part with eO stuck-at-O.

The proposed circuit is shown in Figure 2. It can be seen that eO stack-at-0 is detectable because

e0 (good part = b'l', bad part stuck-at-O)

Vdd

out (good part=b'O',

e2 (=b'O') test-pd-en

(= b'O'),

Fig. 2 Fully testable tri-mux that...