Browse Prior Art Database

EFFICIENT SYMMETRIC FREQUENCY DIVIDER BY 3

IP.com Disclosure Number: IPCOM000008216D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2002-May-28
Document File: 3 page(s) / 93K

Publishing Venue

Motorola

Related People

Yuval Itkin: AUTHOR [+2]

Abstract

This design uses both the rising edges and the falling edge of a clock signal to divide the clock frequency by three, with a 50% duty cycle.

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M-LA Technical Developments

EFFICIENT SYMMETRIC FREQUENCY DIVIDER BY 3

by Yuval ltkin and Shai Kowal

  This design uses both the rising edges and the falling edge of a clock signal to divide the clock frequency by three, with a 50% duty cycle.

  To divide by three the operating principle is based both on positive and negative clock levels. The need for 50% duty cycle forces the output signal to be set at positive clock edges, and to be cleared on negative clock edges. This design uses this principle in two paths composed of three stages on each path.

  Referring to the schematic diagram of Figure 1, the input clock signal is sent along two paths, each path composed of an SR latch, a D-type latch and another SR latch. The SR latches are shared for both paths. The upper path, referred to as the "SET" path, is combined with the "SET" section of the two SR latches, and D-type latch, while the second path, referred to as the "RESET" path, is combined with the "RESET" section of the SR latches and the D-type latch. The SET path uses the low-high-low clock sequence, while the RESET path uses the high-low-high clock sequence. Together the SET and the RESET paths combine 6 clock levels which

are three clock cycles. The principle is based on one master-slave stage and one master only stage, connected in series as a sequencer, so that the master-slave value depends on the master-only value, and vice versa. Figure 2 shows the expected waveforms, obtained by simulation, at the node...