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Method for a silicon-embedded 3GIO pin flexibility feature

IP.com Disclosure Number: IPCOM000008222D
Publication Date: 2002-May-28
Document File: 2 page(s) / 72K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a silicon-embedded 3GIO pin flexibility feature. Benefits include improved functionality and improved designer productivity.

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Method for a silicon-embedded 3GIO pin flexibility feature

Disclosed is a method for a silicon-embedded 3GIO pin flexibility feature. Benefits include improved functionality and improved designer productivity.

Background

              The 3GIO interface is being developed for a possible future replacement to the slower PCI/PCI-X interface. Built into the specification is the concept of lanes. Each data lane (signal pair) provides a data channel of 2.5-Gb/sec frequency or roughly 200-MB of data throughput. According to the specification, configurations of 1x, 2x, 4x, 8x, 12x, 16x, 32x and so on are to be supported.

Description

              The disclosed method is a feature that enables flexibility of associating a pin pair with a lane on a 3GIO silicon device. Each pair of 3GIO pins are programmed to a lane other than the default by preprogramming the chip using one of the following methods:

·        EEPROM

·        Configuration cycles

·        Shared configuration pins

·        MDIO

·        Some other method

              For example, a layer of multiplexers can be added between the wire lane byte register and its internal byte location (see Figure 1). This layer enables any pin pair (lane) to map to any internal byte lane (byte). The illustration shows only the incoming 3GIO path. The outgoing 3GIO path requires a similar multiplexing scheme before its serializing registers.

              Data may be multiplexed with or without the use of registers or with some other multiplexing scheme.

Advantages

              The disclosed method provides advantages, including:

·        Improve...