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Method for embedding passive components in the PTHs of an IC package

IP.com Disclosure Number: IPCOM000008236D
Publication Date: 2002-May-29
Document File: 4 page(s) / 154K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for embedding passive components in the plated throughholes (PTHs) of an integrated circuit (IC) package. Benefits include improved signal quality and improved performance.

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Method for embedding passive components in the PTHs of an IC package

Disclosed is a method for embedding passive components in the plated throughholes (PTHs) of an integrated circuit (IC) package. Benefits include improved signal quality and improved performance.

Background

              As processor speeds increase and die size shrinks, requirements grow for lower inductance between a capacitor and die to enable high-frequency operation. The risk of uncontrolled impedance must be minimized as the high-speed signal passes through the vertical portion of the IC package interconnect.

      The conventional solution has the following characteristics:

·        Adds more capacitors to reduce the overall inductance

·        Adds cost

·        In some cases, has insufficient physical space to accommodate additional capacitors

              Alternative conventional technologies place the capacitors inside the thick core after cutting out large throughholes, such as with embedded capacitors. These solutions result in large expansion coefficient mismatches and add high capacitance on the silicon die.

              Conventionally, capacitors that fit the PTH have metal pads at two opposite ends serving as one polarity of the capacitor and the sidewall of the capacitor to serve as the other polarity.

General description

      The disclosed method embeds passive components in the PTHs of an IC package (see Figure 1). The correct choice of dielectric constant and thickness of the dielectric material enables the inserted component to provide a controlled impedance path for signal lines through the vertical portion of the package.

              The disclosed method may be produced using the following steps (see Figures 2 and 3):

1.      Pin-shaped capacitors (capacitors built around wires) start with conductive wires, such as copper, molybdenum. 

2.      Deposit thin dielectric material with high dielectric constant around the wire.

3.      Deposit conductive layers around the dielectric layer creating capacitors, such as copper.

4.      Cut the wires to a predetermined length, such as equal to the thickness of IC package substrate core.

5.      Insert the pin-capacitor into the PTHs in the IC package core (typically, a PCB). The pin outer conductive layer can be conductively attached to the PTH wall by pressure or through metallurgical joint-like solders

6.      Conventional build-up of a dielectric/metal layer with microvia process c...