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Browse Prior Art Database

Method for Increasing I/O Count on a Silicon Component Utilizing Star-Shaped Land Pad Arrangements

IP.com Disclosure Number: IPCOM000008243D
Publication Date: 2002-May-29
Document File: 1 page(s) / 22K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for increasing the number of signal I/Os on a component package, while still using a four-layer motherboard. Benefits include substantial cost savings by maintaining a smaller package size.

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Method for Increasing I/O Count on a Silicon Component Utilizing Star-Shaped Land Pad Arrangements

Disclosed is a method for increasing the number of signal I/Os on a component package, while still using a four-layer motherboard. Benefits include substantial cost savings by maintaining a smaller package size.

Background

The number of signal I/Os has increased with successive chipset generations. In addition, the interface speed for each generation has increased, requiring the allocation of more power delivery balls. More delivery balls ensure excellent return paths for signal balls, and provide robust power delivery for the silicon component. Currently, the only way to add I/Os to a component is by increasing the package size and/or the I/O depth on the package. This strategy increases the cost of the component, as well as the motherboard.

General Description

The disclosed method increases the number of signal I/Os by using a gridless BGA land pad and star-shaped land patterns on the package footprint (see figures in the attached presentation). This method can be applied to any BGA package development. By mixing star-shaped combinations (~1mm ball pitch arrays) of standard ball pads, a complex and repeatable pattern of lands is created, which optimizes ball spacing, motherboard power delivery, and signal escape opportunities (breakout) from the BGA package. The desired spacing of the mixed land sizes is dictated by the PCB line width and spacing geometries used in circuit bo...