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Browse Prior Art Database

TEST STRUCTURE AND METHOD

IP.com Disclosure Number: IPCOM000008249D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-May-30
Document File: 1 page(s) / 43K

Publishing Venue

Motorola

Related People

John J. Mangle: AUTHOR

Abstract

Memory circuits consist of arrays of identical cells, each containing the same elements, such as transistors or resistors. The operation of the cell depends on the physical dimensions of the elements, such as transistor width or length, or contact size.

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m MOTOROLA Technical Developments

TEST STRUCTURE AND METHOD

by John J. Mangle

  Memory circuits consist of arrays of identical cells, each containing the same elements, such as transistors or resistors. The operation of the cell depends on the physical dimensions of the elements, such as transistor width or length, or contact size.

  Memory circuits are often tested using "bit maps" in which a display is created showing the electrical performance of the cells of the array according to their physical location. Normally, one attempts to produce memory arrays with consistent, identical elements.

I propose to intentionally vary the dimensions of device elements as a function of their location, so

that the dimension of some element is proportional to its position in the array. For example, consider a three-by-three array of cells. Each cell includes some element having characteristic dimensions W and L.

  Let the array be drawn so that W increases as we move to the right, and L increases as we move upward.

  With this structure, the bit map showing electri- cal performance as a function of location automati- cally produces a display of performance vs. L, a display of performance vs. W, and a display of the effect of various W/L combinations.

1 L

0 Matorda, Inc. ,997 September 1997

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