Browse Prior Art Database

ENHANCED PLL CARRIER RECOVERY CIRCUIT

IP.com Disclosure Number: IPCOM000008254D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-May-30
Document File: 2 page(s) / 74K

Publishing Venue

Motorola

Related People

Terance B. Blake: AUTHOR

Abstract

Phase locked loops can be used for RF carrier recovery. The flip-flop phase detectors and lowpass filters in such loops tend to idle midway between the supply voltage rails when no RF signal is present. The signal acquisition range, time, and sensitivity are influenced by how far from the idle voltage the VCO input voltage needs to be. This is dependent on ~VCO part variations, temperahue, and the desired RF signal frequency. The higher RF signal frequencies used in many of today's systems can put greater burdens on these systems, due to frequency tolerance requirements. The initial signal acquisition, fade recovery time, and over-tempera- ture performance could all be improved if the ideal PLL idle frequency could be measured and controlled.

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0 M MO-LA

Technical Developments

ENHANCED PLL CARRIER RECOVERY CIRCUIT

by Terance 6. Blake

INTRODUCTION

  Phase locked loops can be used for RF carrier recovery. The flip-flop phase detectors and lowpass filters in such loops tend to idle midway between the supply voltage rails when no RF signal is present. The signal acquisition range, time, and sensitivity are influenced by how far from the idle voltage the VCO input voltage needs to be. This is dependent on ~VCO part variations, temperahue, and the desired RF signal frequency. The higher RF signal frequencies used in many of today's systems can put greater burdens on these systems, due to frequency tolerance requirements. The initial signal acquisition, fade recovery time, and over-tempera- ture performance could all be improved if the ideal PLL idle frequency could be measured and controlled.

DESCRIPTION

  The idle voltage from the flip-flop is deter- mined by the upper and lower voltage rails of the CMOS output stage, typically 5 volts and 0 volts
(2.5 volts idle into the VCO). The idea is to add an external CMOS inverter stage that has the upper and lower voltage rails controlled by digital to

analog converters. Thus a VCO idle level of 3.5 volts can be set by a 5 volt upper rail and a 2 volt lower rail.

  The loop response can also be controlled by the distance between the rails. Greater distance provides faster response and shorter distance provides a slower response. Thus a VCO idle level of 3.5 volts with a m...