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Method for a buffer-strengths based data strobe delay generator

IP.com Disclosure Number: IPCOM000008259D
Publication Date: 2002-May-30
Document File: 2 page(s) / 109K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a buffer-strengths based data strobe delay generator. Benefits include improved functionality.

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Method for a buffer-strengths based data strobe delay generator

Disclosed is a method for a buffer-strengths based data strobe delay generator. Benefits include improved functionality.

Description

              The disclosed method is a procedure for stressing buffer timings during AC timing tests (NG-ACIO), and output voltage levels test (VoxBist). The clock-to-out time (TCO) is a function of buffer strength. If data and strobe buffer strengths can be different, a delta in TCO can be introduced in either direction, and timing can be stressed in either direction. Changing buffer strengths also changes signal levels and integrity.

              To realize the buffer-strengths based data strobe delay generator, two steps are required:

1.      Separate routing of data and strobe buffers pull-up and pull-down bits

2.      External bit programmability of RCOMP control registers, bypassing any typical functional state machine controls from the core

      With the availability of these two defect and fault tolerance features, a part can be forced to function as a slower or faster part on data or strobe precisely for certain cycles. Suddenly an extremely powerful tool is available to component or system test engineers for stressing bus timings. Typically on a 400-MHz bus, measuring at VREF specification level, timing delays of approximately 500 ps can be realized across skew. As busses scale upwards (assuming that granularity remains the same 14 bits), precision automatically improves. Used in conjunction with IOPROCMON, this...