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A Method for Suppressing Parasitic Bipolar Effects in Partially-Depleted and Fully-Depleted SOI-CMOS SRAM Arrays Through the Utilization of a False-Write Strategy

IP.com Disclosure Number: IPCOM000008304D
Publication Date: 2002-Jun-04
Document File: 2 page(s) / 25K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method which uses a high frequency bitline voltage-pulse (e.g. false-write) that occurs at a fixed period of time between read and write accesses to the memory array. The time and frequency of false-write can be tailored to a specific cache size or operational specification. Benefits include the potential to increase high-performance/high-margin chip yield.

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A Method for Suppressing Parasitic Bipolar Effects in Partially-Depleted and Fully-Depleted SOI-CMOS SRAM Arrays Through the Utilization of a False-Write Strategy

Disclosed is a method which uses a high frequency bitline voltage-pulse (e.g. false-write) that occurs at a fixed period of time between read and write accesses to the memory array. The  time and frequency of false-write can be tailored to a specific cache size or operational specification. Benefits include the potential to increase high-performance/high-margin chip yield.

Background

SRAM and sense amplifier arrays in partially depleted silicon-on-insulator (PDSOI) and fully depleted silicon-on-insulator (FDSOI) technologies suffer from performance problems due to body-bias fluctuations (body-effect) in the CMOS devices that comprise them, and the non-scaling build-up of a critical voltage differential in the sense amplifiers. In PDSOI CMOS processes (and to a much smaller extent, in FDSOI CMOS), the body-voltages of NFET and PFET devices fluctuate because they do not have a body contact, but instead reside on an insulating layer of oxide. Devices are created in a thin silicon film that rests on this insulating layer, and their body-effect is a strong function of the thin film’s thickness, its doping concentration and profile, and the depth of the source and drain node’s depletion.

This variation in body voltage affects the performance of the device in several ways, one of which is that the body source and body drain diodes may become forward or reverse biased.  When forward biasing occurs on wordline NFETs in an SRAM cell, the charge accumulated in each device’s body may be discharged onto the bitline when voltage drops below the voltage on the body during a write or read operation. This charge can affect both the accuracy and timing of data written into a cell, or increase the time for a critical voltage differential to build-up between the two bitlines for a successful read operation.

General Description

The high-frequency false-write of the disclosed method eliminates any build-up of charge in the word-line NFET’s body by forward biasing the NFET’s diode that the bitline ‘sees’. This eliminates excess parasitic bipolar current that would otherwise be dumped onto the bitline during the next read or write operation, and which would otherwise result in significantly...