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Method for external bus testing using an on-die pattern generator/checker

IP.com Disclosure Number: IPCOM000008308D
Publication Date: 2002-Jun-04
Document File: 5 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for external bus testing using an on-die pattern generator/checker. Benefits include improved functionality, improved performance, and enhanced test environment.

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Method for external bus testing using an on-die pattern generator/checker

Disclosed is a method for external bus testing using an on-die pattern generator/checker. Benefits include improved functionality, improved performance, and enhanced test environment.

Background

              As component-to-component bus speeds increase and circuit boards get smaller, testing these bus connections in a high-volume manufacturing (HVM) test environment is becoming increasingly difficult and in some cases impossible.

              Conventional testing is accomplished by two methods. The first is using a platform probing station that lands test probes on circuit boards to test opens and shorts and basic component-to-component bus functionality. The second method is using software to generate the pattern when the system was booted and operational.

              Conventional testing methods that require the system to boot an operating system in an HVM test environment are expensive and time consuming. The probe method of testing is proving too invasive to high-speed bus testing. This method is expensive. In some cases, this method is impossible with smaller, more densely populated circuit boards.

General description

              The disclosed method is an on-die standalone I/O pattern generator used in system-level bus testing in an HVM environment. The goals of the disclosed method include:

·        Reduced platform test time

·        Reduced bus-speed restrictions on invasive probing

·        Platform-level test point access and availability

·        Test reduction/elimination

              The pattern generator is used in platform test to perform tests ranging from simple opens and shorts tests on the bus to complex pattern transfers. Testing a bus between components enables testing of the following items:

·        Entire bus

·        Silicon

·        Motherboard

·        Interconnect

·        Power delivery

              The key elements are:

·        User configurable I/O bus pattern generator for testing interconnections between components at the platform level

·        Pattern generator not dependant on component core circuitry or core frequency

Advantages

The disclosed method provides advantages, including:

·        Time savings in test and debug due to use without booting an operating system on the platform

·        Use in debugging and testing cases where the system is too unstable to boot an operating system and run system software

·        Capability to send or receive data on the bus at full bus speed and to check for error conditions indicating bus failure

·        Capability for the user to configure the patterns and the mode of operation of the pattern generator

·        Use in variable bus-frequency testing

·        Improved test coverage compared to software-based pattern generators

·        Improved flexibility to the user in pattern generation on the bus because the pattern generator is not connected to the core of the chip and does not follow a particular bus protocol

Detailed description

              The disclosed method is an I/O bus pattern generator that is comprised of three levels of circuits (see Figure 1). Each I/O buffer contains pattern buffer a...