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Method to transfer packets using write bursting

IP.com Disclosure Number: IPCOM000008312D
Publication Date: 2002-Jun-04
Document File: 3 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to transfer packets using write bursting. Benefits include improved performance.

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Method to transfer packets using write bursting

Disclosed is a method to transfer packets using write bursting. Benefits include improved performance.

Background

              One of the problems facing conventional high-performance adapters using direct memory access (DMA) is scaling small packet transmission throughput with substantial increases in wire bandwidth. One key factor making small packet scaling difficult is per-packet transmit DMA latencies. The total time to transmit a packet is made up of two major factors. One factor is the time to perform the data transfer across the bus. The second factor is any delays (such as, latencies) incurred before or during the data transfer.

              The conventional process (see Figure 1) begins with the operating system indicating to the adapter’s software driver that it has a packet to send. The driver creates a description of the packet to send (D). The description is typically referred to as a descriptor. The driver then indicates to the adapter that it has a new packet descriptor (D) ready to be transferred from the host to the adapter. The driver performs a PIO Write (W) to indicate to the adapter the presence of the new descriptor.

              The adapter initiates a DMA from main memory to fetch the description of the packet to the adaptor for processing (DMA 1). The adapter incurs the first DMA related latency in the transfer process labeled L1.

              The adapter waits for the first DMA to complete. When completed the adaptor has the information it needs to fetch the packet from the host. This typically includes the location and the size of the packet. The adaptor initiates a second DMA to fetch the packet from the host. The second DMA is illustrated as DMA 2. The packet header (H) and the packet payload (P) are located in one contiguous area in the host memory requiring only one descriptor and only one DMA. In some operating systems, the header (H) is located in separate location, requiring an additional descriptor and an additional DMA.

              The total time to transmit a small packet is the sum of the PIO Write, the combi...