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A METHOD FOR OPTIMIZED LEVELIZATION IN CYCLE-BASED SIMULATION

IP.com Disclosure Number: IPCOM000008341D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-07
Document File: 3 page(s) / 147K

Publishing Venue

Motorola

Related People

Mike Braddock: AUTHOR [+3]

Abstract

Levelization is a logic simulation technique where each gate or logic assignment is evaluated once per time period, just prior to when its output is needed. This is in contrast to event-driven simula- tion, where logic is evaluated whenever its input changes. While event-driven simulation is more general, levelizatiqn permits higher-performance because there is no overhead associated with main- taining an event queue. Most cycle-based simulator implementations are based on levelization techniques.

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Page 1 of 3

Technical Developments

A METHOD FOR OPTIMIZED LEVELIZATION IN CYCLE-BASED SIMULATION

by Mike Braddock, Richard Duerden, and Jeff Freeman

INTRODUCTION

  Levelization is a logic simulation technique where each gate or logic assignment is evaluated once per time period, just prior to when its output is needed. This is in contrast to event-driven simula- tion, where logic is evaluated whenever its input changes. While event-driven simulation is more general, levelizatiqn permits higher-performance because there is no overhead associated with main- taining an event queue. Most cycle-based simulator implementations are based on levelization techniques.

  Conventional levelization produces a static list of evaluations which are executed in sequence. For a given execution pass through the list, however, not all of the evaluations are actually necessary. An example of this would be when using a four-input multiplexer, which at any particular point in time only requires one of its four inputs to be evaluated. A method is described here to optimize levelization for improved performance by taking advantage of these situations.

  In this description, the Verilog hardware model- ing language and the 'C' programming language are used, however the concepts presented are not limited to those languages.

DESCRIPTION

  Levelization performance can be improved by evaluating some of the model logic on a conditional basis. This is accomplished by moving portions of the levelized code into nested blocks whose evalua- tion is controlled by some condition. An additional constraint on such nesting is introduced by cases where the output of a continuous assignment is needed in multiple places.

  The goal of the optimization is to generate 'C' code which evaluates each required continuous assignment one time, at the lowest-level "block" common to all blocks which require the continuously assigned value. This is done individually for each time period. See Figure I.

II Pseudo code using //optimized levelization:

if (qwerty)

1

1 cal = a 8 b; ca2=cld;
if (car)
x = ca2; else
begin f-Ah; ca3=eAf; y = ca3; end
z = caz;

1

Fig. 1 Translations using conventional and optimized levelizations

0 Motorola. 1°C. ,997 I70

// Verilog code (segments):

N Continuous assignments assign
cal = a & b,
ca2=cld,
ca3=eAf,
f ="h;

II Procedural logic if (qwerty)
begin
if (Cal)
x = ca2; else
y = ca3:
* = ca2;
end

II Pseudo code using II conventional levelization:

cat = a & b; ca2 = c I d: f = Ah ca3=efif;

if WeW

I

if (Cal) x = ca2; else
y = ca3; * = ca2;

1

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0 M MO-LA

Technical Developments

  To accomplish this, blocks are identified and associated with the continuous assignments they need, and then a single best-choice block is deter- mined for each continuous assignment. At code generation time, continuous assignments are printed on a per-block basis. The following paragraphs describe this process in more detail. Refer to Figure 2...