Browse Prior Art Database

METHOD AND APPARATUS TO HIDE MEMORY LATENCY

IP.com Disclosure Number: IPCOM000008345D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-07
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

Bryan Marietta: AUTHOR [+4]

Abstract

An in-line cache is a cache that is logically between the processor and the system bus. It is used to improve system to processor bandwidth by caching data and allowing increased interface frequency, while reducing system bus bandwidth requirements. If there is a cache miss at the in-line cache a memory system read operation is required. This read operation has a long latency which ties up the processor to in-line cache bus in a pipelined system. It is desirable to use this latency period for other bus operations without terminating the memory read. The PowerPC 60X bus architecture is assumed in this paper.

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0 M MO-LA

Technical Developments

METHOD AND APPARATUS TO HIDE MEMORY LATENCY

by Bryan Marietta, C.S. Hui, Jikku Venkatramani, and Hai Bui

ABSTRACT

  An in-line cache is a cache that is logically between the processor and the system bus. It is used to improve system to processor bandwidth by caching data and allowing increased interface frequency, while reducing system bus bandwidth requirements. If there is a cache miss at the in-line cache a memory system read operation is required. This read operation has a long latency which ties up the processor to in-line cache bus in a pipelined system. It is desirable to use this latency period for other bus operations without terminating the memory read. The PowerPC 60X bus architecture is assumed in this paper.

INTRODUCTION

  A typical in-line cache allows the processor to access data from system memory or from the in-line cache over the processor bus. If the data resides in the in-line cache no system bus activity is neces- sary. If the data must be retrieved from system memory a system bus cycle results, tying up the processor bus until the operation completes. Figure 1 shows a situation where a read operation from the processor misses in the in-line cache. All signals in the Figures are active high. The operation start is indicated by the assertion of the processor transfer start (TS) signal. The ,address bus busy signal (ABB) indicates when the bus is busy and can not be used for other processor operations. The processor bus is released when the address is acknowledged via the AACK signal, Two cycles after AACK a new request can be issued.

  The read is forwarded to the system bus (using the same bus protocol) and the processor bus kept busy until it completes successfully and data can be returned to the processor. The subsequent read oper- ation generates a hit in the in-line cache must wait

until the previous operation is completed because the cache ram is still busy reloading returning data and is unable to receive a new address. When the data return is completed the cache hit can be serviced.

OPERATION

  The in-line cache controller contains a number of data buffers that allow the controller to temporarily store data returned from the system. Figure 2 shows the intended use. As before, the processor starts a read operation by as...