Browse Prior Art Database

MULTI-PORT RAM WORKSPACE FOR A SINGLE-CHIP MICROCONTROLLER

IP.com Disclosure Number: IPCOM000008346D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-07
Document File: 2 page(s) / 125K

Publishing Venue

Motorola

Related People

Raymond L. Barrett, Jr.: AUTHOR [+3]

Abstract

The Multi-Port RAM Workspace for a Single- Chip Microcontroller utilizes a multi-port RAM, preferably in a single-chip environment, to produce a set of workspaces (equivalent to a set of register banks) allowing support for the typical RISC-like feature of a large bank of large registers without incurring the overhead delays associated with rapid context switching. Prior art has utilized the workspace concept, but incurred a performance penalty implementation from the isolated CPU and RAM structures available twenty years ago, forcing abandonment of the concept. Herein is a new architecture.

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MO7VROLA Technical Developments

MULTI-PORT RAM WORKSPACE FOR A SINGLE-CHIP MICROCONTROLLER

by Raymond L. Barrett, Jr., Barry Herold and James Mittel

ABSTRACT

  The Multi-Port RAM Workspace for a Single- Chip Microcontroller utilizes a multi-port RAM, preferably in a single-chip environment, to produce a set of workspaces (equivalent to a set of register banks) allowing support for the typical RISC-like feature of a large bank of large registers without incurring the overhead delays associated with rapid context switching. Prior art has utilized the workspace concept, but incurred a performance penalty implementation from the isolated CPU and RAM structures available twenty years ago, forcing abandonment of the concept. Herein is a new architecture.

  The Multi-Port RAM Workspace for a Single- Chip Microcontroller is composed of standard components connected to perform a register work- space context switching environment most suitable for embedded micro-controllers in a single-chip environment.

  Prior art, in the form of the T.I. 9900 family of microprocessors, employed a context switching principle utilizing a hardware implemented work- space pointer register to select a base address in an external RAM memory

  In the T.I. architecture, access to the register workspaces in the common memory map are provided by the common address bus and a data bus pins on the MPU, which are also used to access

program and data spaces. The supporting hardware manages the context-switching "Workspace Pointer" register so that a change of context leaves one RAM-based register context without requiring a stacking mechanism, swap space, etc. usually required for context switching. Due to the common buses, however, some of the time savings of the context switch are lost by the Read/Write character- istics of the Address/Data Bus access method.

  Modern microcontrollers have been evolving toward RISC-style architectures, which typically utilize a register bank consisting of a large number of large registers, and incur a heavy time penalty during a context switch, to store and restore the context. In addition, a large percentage of applica- tions for these micro-controllers are interrupt-driven, producing many context-switch operations.

  What is needed is an architecture that combines the rapid context-switching capabilities of the work- space pointer concept, without incurring the penalties associated with the single address bus/data bus pair.

  To produce an architecture which provides rapid context-switching, we utilize the workspace pointer in a hardware register, much like the prior art, but we provide a multi-port RAM, illustrated in Figure
1.0, with the capability of writing to RAM from one bus (called the Y bus), while reading from RAM on two other buses (called the A and B bus respective- ly), so tha...