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Improved Arithmetic Unit for JBIG Coding

IP.com Disclosure Number: IPCOM000008349D
Original Publication Date: 2002-Jun-07
Included in the Prior Art Database: 2002-Jun-07
Document File: 3 page(s) / 231K

Publishing Venue

Motorola

Related People

Colin MacDonald: AUTHOR [+2]

Abstract

The ITU-T Specification T.82 Information Technology Coded Representation of Picture and Audio Information Progressive Bi-Level Image Compression prepared by the Joint Bi-level Image experts Group (JBIG) describes the registers and flow for compliant arithmetic coding. This article describes various modifications to registers and flow that give a hardware coding engine reduced cycle time but maintain compatibility with the standard. The hardware coding engine takes two clocks to code each pixel or three if a movement of coded data is involved.

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Improved Arithmetic Unit for JBIG Coding

Colin MacDonald, Thomas Volpe

Abstract:

The ITU-T Specification T.82 “Information Technology – Coded Representation of Picture and Audio Information – Progressive Bi-Level Image Compression” prepared by the Joint Bi-level Image experts Group (JBIG) describes the registers and flow for compliant arithmetic coding. This article describes various modifications to registers and flow that give a hardware coding engine reduced cycle time but maintain compatibility with the standard. The hardware coding engine takes two clocks to code each pixel or three if a movement of coded data is involved.

The ITU-T Specification T.82 describes registers and processing flows to implement a JBIG compatible encoder and decoder. However, the processing flows associated with the coders include a normalization loop that may iterate up to fifteen times. Consequently, a direct hardware implementation of the specification would result in an inefficient coder that could take fifteen clocks to process one pixel. But modifications, particularly to registers and the flow associated with normalization, enable the implementation of a hardware coder with a two/three clock coding cycle.

In JBIG processing, normalization is frequently performed on two registers (A, C) after an arithmetic operation. If required, the amount of normalization required varies between one and fifteen shifts. Each shift of the C Register equates to the transfer of a coded data bit so that normalization may require zero, one or two bytes of coded data to be transferred.  

 

Figure 1 Original and Improved Arithmetic Flows

Figure 1.0 shows two flows, the upper one represents the flow described by the ITU-T specification and the lower represents the improved flow used to implement a JBIG coding engine in hardware.  The problem with the upper flow is that it performs normalization iteratively. Implementing this exact flow in hardware directly using synchronous logic would require a clock cycle for each normalization shift up to a maximum of 15 clocks. The improved flow performs normalization in one clock if no data movement is required or two clocks if it is.

Normalization performed in two stages allows the alignment of data for transfer. This process is explained using a simplified diagram of an improved encoder (Figure 2.0).

 

Figure 2 Improved Arithmetic Unit – Encoder

The total amount of normalization required is based on the value in the A Register [1] following an arithmetic operation. Renorm Shift [2] calculates the total shift required to complete normalization based on the value of the A Register and places the value onto RSHFT [3:0]. The C Register [6] is shifted using the 36-bit C Barrel Shifter [5]. The C Register outputs feed C Barrel Shifter inputs via CBS_IN (35:0). The C Barrel Shifter moves data left by the amount specified on CSHIFT (3:0) and the shifted data is stored back in the C Register (35:0) via CBS_OUT (35:0). C Register bit positions 34 through 1...