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A METHOD FOR A MULTI-TIME-SLOT LEVELIZED COMPILED HARDWARE SIMULATOR

IP.com Disclosure Number: IPCOM000008353D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-10
Document File: 4 page(s) / 152K

Publishing Venue

Motorola

Related People

Jeff L. Freeman: AUTHOR

Abstract

On the 68060 design, we had about 2 million vectors to run against the hardware model of the chip. It would take more than three weeks to do this using the Verilog-XL simulator from Cadence because at the time, the Verilog simulation was about 0.4 Hz. Fewer verification cycles lead to lower confidence in a correct design. Mask shop was delayed many months because design errors came up so late in the design process. Even after first silicon, functional design errors were found which led to many more mask revisions of the 68040.

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MOTVROLA Technical Developments

A METHOD FOR A MULTI-TIME-SLOT LEVELIZED COMPILED HARDWARE SIMULATOR

by Jeff L. Freeman

INTRODUCTION

  On the 68060 design, we had about 2 million vectors to run against the hardware model of the chip. It would take more than three weeks to do this using the Verilog-XL simulator from Cadence because at the time, the Verilog simulation was about 0.4 Hz. Fewer verification cycles lead to lower confidence in a correct design. Mask shop was delayed many months because design errors came up so late in the design process. Even after first silicon, functional design errors were found which led to many more mask revisions of the 68040.

  The Multi-Time-Slot Levelized compiled simulator (sim60), was developed using the 68040's verification problem (not enough verification cycles) as a testcase. The 68040 has a four-phase clocking system, so that is where this method of using discrete time slots began.

DESCRIPTION

  Sim60 (also known as sim50) is a "C" level implementation of the integer unit of the 68040. All of the Verilog code of the 68040 integer unit was hand translated to "c" code. Figure 1 is an example of translating Verilog to "c".

  In this Iigure, note that the event is "tl", the first of four clock phases of the 68040. The "-1" represents one simulation time unit into the "tl" clock phase.

Verilog example: always Qposedge tl #l begin statement
statement

C translation: void tl-event-l-EARESO() begin
statement statement

end C translation syntax for event blocks:

t[l...4]-event-[O...lO]-MODULE#() begin
statements
statements

end

where posedge of a clock is 0 and negedge of a clock is 10 and the delay of the block is added to this value.

Fig. 1 Methodology of Translation

Here the "t" was the clock prefix, the O-n was the delay into the clock phase, MODULE was the

name of the logic block being simulated, and the final # allowed for multiple time slots to be distin- guished within a common logic block. Figure 2 shows the program organization:

end

u1 Mommla. ,"E. ,997 192

September 1997

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M-LA Technical Developments

@

"C" source

I I

+ pla?.c files

"C" source + pla?.c file

jGk+---+ compilation 1 (fast)

dynamically reads 30 Meg binary pla tiles for decode table lookup

Fig. 2 Program Organization

A Per1 script "main.p" reads in all the hand- translated "C" descriptions of the 68040 integer

PLA's or creates large "C" source lookup tables,

unit, sorts the time events, and produces a "mainc"

The latter (Sim60H) uses about 30 megabytes of memory and is very fast since it just has to index "C" program source. For the PLA's of the 68040 into a static array.
integer unit, another Per1 script called "e2c.p" reads
the espr...