Browse Prior Art Database

A 3V - 5V LEVEL SHIFTER

IP.com Disclosure Number: IPCOM000008354D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2002-Jun-10
Document File: 2 page(s) / 87K

Publishing Venue

Motorola

Related People

Debbie Beckwith: AUTHOR

Abstract

A 3V - 5V level shifter, which accepts voltages on the "IN" port in the range of 2.7V < VCCA < 3.6V, and is designed to produce voltages on the "OUT" port in the range of 4.5V < VCCB < 5.5V, will be discussed and is shown in Figure 1.1. The invention is designed for interfacing circuitry operating at two different voltages. It is necessary to have the capability to interface circuitry operating at two different voltages to integrate the lower voltage technologies into the mainstream integrated circuit sales.

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MOTOROLA Technical Developments

8

A 3V - 5V LEVEL SHIFTER

by Debbie Beckwith

BACKGROUND

A 3V - 5V level shifter, which accepts voltages on the "IN" port in the range of 2.7V < VCCA <
3.6V, and is designed to produce voltages on the "OUT" port in the range of 4.5V < VCCB < 5.5V, will be discussed and is shown in Figure 1.1. The invention is designed for interfacing circuitry operating at two different voltages. It is necessary to have the capability to interface circuitry operating at two different voltages to integrate the lower voltage technologies into the mainstream integrated circuit sales.

PURPOSE

The requirements for a 3V - 5V level shifter

include the ability to protect against ICC leakage cur- rent due to the gate of the p-channel device powered at the higher voltage (VCCB) being driven by a device powered at (VCCA) and therefore only having the ability to pull the gate node to VCCA. When the gate node of the p-channel device powered at VCCB is pulled to the VCCB supply voltage to inhibit ICC leakage current, the 3V - 5V level shifter must protect the lower voltage power supply from corruption due to the turning on of the p-channel device powered at VCCA, and whose gate voltage is at VCCA, as well as turning on the parasitic pnp transistor associated with the pmos device. Other requirements include minimal added delay, minimal added layout area, and minimal power dissipation. This invention meets all of the above criteria.

Fig. 1.1 3V - SV Level Shifter

0 hklwro,a, I"C. ,997 202 September 1997

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MOTOROLA Technical Developments

SOLUTION

  The circuit...