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RELIABLE LEADFRAME DESIGN FOR CONTACTLESS SMART CARD AND PLASTIC PACKAGING

IP.com Disclosure Number: IPCOM000008362D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-11
Document File: 2 page(s) / 101K

Publishing Venue

Motorola

Related People

Jean-Marc Delbecq: AUTHOR [+5]

Abstract

The radio frequency (RF) personal identifica- tion (ID) card and contactless smart card markets have been enjoying a high growth rate in the recent years. One of the issues to develop superior, low cost manufacturing technologies and capabilities is manufacturing yield (quality). Of the yield issues, interconnect (i.e., solder joint, conductive adhesive, etc.) failure or poor card surface (pitting, voiding, warpage, bow, etc.) are the two major concerns observed in the card fabrication. In the existing ID/smart card lamination process developed by Indala, an IC, a chip capacitor, a chip resistor, two leadframes, and a coil are sandwiched between two polyvinyl chloride (PVC) layers (See Figure I). During this lamination process, pressure forces exerted by the soft PVC flow, e.g. PVC tends to push the two leadframes apart (A and B in Figure 2), resulting in severe stresses in the solder joints. These process-induced stresses can easily cause the solder joint to crack.

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MOTOROLA Technical Developments

RELIABLE LEADFRAME DESIGN FOR CONTACTLESS SMART CARD AND PLASTIC PACKAGING

by Sean X. Wu, Jean-Marc Delbecq, Chao-pin Yeh, Winnie Leung and Karl Wyatt

1 INTRODUCTION AND BACKGROUND

  The radio frequency (RF) personal identifica- tion (ID) card and contactless smart card markets have been enjoying a high growth rate in the recent years. One of the issues to develop superior, low cost manufacturing technologies and capabilities is manufacturing yield (quality). Of the yield issues, interconnect (i.e., solder joint, conductive adhesive, etc.) failure or poor card surface (pitting, voiding, warpage, bow, etc.) are the two major concerns observed in the card fabrication. In the existing ID/smart card lamination process developed by Indala, an IC, a chip capacitor, a chip resistor, two leadframes, and a coil are sandwiched between two polyvinyl chloride (PVC) layers (See Figure I). During this lamination process, pressure forces exerted by the soft PVC flow, e.g. PVC tends to push the two leadframes apart (A and B in Figure
2), resulting in severe stresses in the solder joints. These process-induced stresses can easily cause the solder joint to crack.

2 FINITE ELEMENT ANALYSIS AND DISCUSSIONS

  To resolve the yield problem, simulation and modeling tools are used to find the root cause(s) and possible solutions. A detailed, comprehensive 3-D tinit element analysis has been performed for the existing lndala ID card design. The results of this analysis show that with the existing design, solder stresses can reach a level that causes solder material to fail. One obvious way to reduce the excessive solder stresses is to reduce lamination pressure. However, with a reduced pressure, the surface quality may suffer. In order to reduce solder

stress while preserving adequate manufacturability and surface quality, a modified design is proposed. As shown in Figure 3, an additional area (a...