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Method for an inverted BGA package for stacking multichip modules

IP.com Disclosure Number: IPCOM000008388D
Publication Date: 2002-Jun-11
Document File: 5 page(s) / 105K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an inverted ball grid array (BGA) package for stacking multichip modules (MCMs). Benefits include improved functionality and improved reliability.

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Method for an inverted BGA package for stacking multichip modules

Disclosed is a method for an inverted ball grid array (BGA) package for stacking multichip modules (MCMs). Benefits include improved functionality and improved reliability.

Background

              Conventional MCMs are obtained by stacking individual die on top of each other. This stacking becomes increasingly difficult as the number of dice in the module increases. Many combinations of dice cannot be easily stacked without a spacer between them if the die layouts are not compatible to stacking. Spacers add to the package height. In addition to spacers, some dice are incompatible because maximum wire lengths are exceeded, especially when stacking high I/O count logic dice with low I/O memory chips. A logic die typically has bond pads on all four sides of the die, which severely limits the die size for stacking.

              Conventional stacking solutions require a perimeter ball array on the top package. A 0.5-mm pitch is required to accommodate an adequate number of I/Os. This solution limits flexibility with existing stacked modules, such as a fully populated ball array. The largest die size and I/O count determine the package size.

              One conventional solution accomplishes package-to-package stacking using a perimeter array of solder balls. However, the strips are not molded before stacking. This approach causes voiding problems and warpage during the molding process. No more than one die can utilize the wirebonding interconnection. All other die must be flip-chip or lead-beam bonded.  For logic die stacking, the high-I/O part must be on top of the stacked package, which causes larger X-Y dimensions as well as thermal issues. This solution does not easily enable testing or burn-in on low-yielding dice. All substrate layers in the package must be highly customized for each die.

              In many multichip modules, burn in is required for one die but not for the other dice. In addition, if a low-yielding die is stacked or known good die (KGD) are not available, the die cannot be tested before stacking. Good die may be lost during burn-in when low-yielding die are determined to be defective, which adds cost to the product.

General description

              The disclosed method assembles a multichip module out of two or more individual packages surface mounted together. The base package is the predominant aspect of the disclosed method.

              A die is mounted onto a substrate, using flip-chip technology (see Figure 1) or a standard die-attach/wire-bond process (see Figure 2). After die attach, a no-flow underfill is applied for flip-chip devices while a wire-bonded chip is encapsulated using a transfer-mold or epoxy-dispense process. The thickness of the die and overmold must be less than the solder ball height of the package after surface mounting.

              The substrate could be constructed with any material used conventionally for assembly substrates, such as:

·        Polyimide

·        BT laminate

·        FR4

·        FR5

              For the base package, substrate routing is ac...