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Method for a microelectronic package with an integrated stiffener

IP.com Disclosure Number: IPCOM000008390D
Publication Date: 2002-Jun-11
Document File: 3 page(s) / 105K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a microelectronic package with an integrated stiffener. Benefits include improved reliability and reduction of defects.

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Method for a microelectronic package with an integrated stiffener

Disclosed is a method for a microelectronic package with an integrated stiffener. Benefits include improved reliability and reduction of defects.

Background

              A similar structure can be produced with a bumpless build-up layer (BBUL) but would involve a major change to the business infrastructure, TPT increase due to serial processing and cost due to yield loss of die. A delay lock loop (DLL) substrate uses similar concepts but has a stiffener on the land side with perforations for contacts (such as lands). This land-side stiffener adds cost and results in stress on the die surface due to coefficient for thermal expansion (CTE) mismatch.

              Conventionally, the problem described above is solved by using flip chip pin grid array (FC-PGA) and (organic land grid array) OLGA packages with a thick core and its resultant disadvantages.

General description

              The disclosed method produces a package with compliant build-up layers on top of the die that is integrated into a stiffener. The key elements include:

·        Process to build up layers on a ring-shaped stiffener that is stretched as a membrane across the opening in the ring

·        Formation of electrical contact between a die and contacts on the membrane, such as by a standard flip-chip attachment process or a no-flow process

·        Encapsulation of the die within the hole in the stiffener by a potting process

Advantages

              The technical advantages of the disclosed method include:

·        Lower...