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Method for fabrication of a low cost and high performance imprinted multilayer substrate/package/board

IP.com Disclosure Number: IPCOM000008391D
Publication Date: 2002-Jun-11
Document File: 7 page(s) / 120K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for fabrication of a low cost and high performance imprinted multilayer substrate/package/board. Benefits include improved functionality, improved reliability, and simplified manufacturing process.

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Method for fabrication of a low cost and high performance imprinted multilayer substrate/package/board

Disclosed is a method for fabrication of a low cost and high performance imprinted multilayer substrate/package/board. Benefits include improved functionality, improved reliability, and simplified manufacturing process.

Background

              As microprocessors increase in speed and decrease in size, requirements are generated for improved power utilization, inductance, and signal integrity. The memory, chipsets and microcontrollers that support the microprocessor must also meet demanding requirements. All requirements must be met with cost-effective solutions. Examples of requirements include:

·        Improved signal rise time and propagation speed

·        Cost-effective solution for the formation of plated through-holes and vias without drilling

·        Carrying requirements for package attributes

·        Reliability requirements associated with power delivery components attached and/or in contact with silicon, ceramic, and/or organic materials

·        Mechanical property requirements for substrates

              Conventionally, the problem described above is solved by the process of record (POR). A number of variations on the POR exist; however, the basic process is comprised of the core process followed by the build-up process.

              The core process is comprised of the following steps:

(Note: The process described is for organic substrates.)

1.      Laminate copper to sheet(s) of organic material

2.      Mechanically drill to form holes in the core

3.      Clean holes

4.      Metalize holes

5.      Fill holes

6.      Planarize the surface

7.      Metalize the surface

8.      Apply the photo resist material

9.      Expose desired pattern on copper using photo tool

10.  Develop the resist material

11.  Etch the pattern on copper

12.  Strip the resist material

The build-up process is comprised of the following steps:

1.      Apply the first build-up layer material to the core

2.      Semi-cure the first build-up layer material

3.      Form vias in the build-up layer material using a laser drill and clean the exposed Cu pads

4.      Plate with copper to metalize the vias and form copper on top surface of first build-up layer

5.      Apply and image the photo resist material

6.      Develop, etch, and strip to form traces/spaces on the surface of the build-up layer

7.      Repeat steps 1-6 until all build-up layers are formed

8.      Apply the solder mask

9.      Develop and etch the solder mask

10.  Finish plating the exposed surfaces with Ni and Au

General description

              The disclosed method is a design and fabrication processes for a low cost and high performance substrate/package using imprin...