Browse Prior Art Database

Method for a programmable-delay synthesizer for DDR memory controllers

IP.com Disclosure Number: IPCOM000008395D
Publication Date: 2002-Jun-11
Document File: 4 page(s) / 138K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a programmable-delay synthesizer for DDR memory controllers. Benefits include improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Method for a programmable-delay synthesizer for DDR memory controllers

Disclosed is a method for a programmable-delay synthesizer for DDR memory controllers. Benefits include improved performance.

Background

              Conventional double data rate (DDR) and DDR II devices use a source-synchronous clocking protocol to transfer data from the memory to the memory controller (see Figure 1). Data (DQ) from memory is captured by the memory controller using a clock (DQS) supplied by the memory devices. The DQS from the memory devices is delayed by the memory controller to capture the data from the memory devices. Uncertainty in this DQS delay circuit adds to the overall setup and hold time for the memory controller.

              The typical delay in a DDR design is approximately a quarter of a DDR clock cycle that can be 800 to 1800 ps. At the same time, the granularity of the delay must be extremely fine (about 15 ps) when compared to the overall delay.

              The ideal setpoint of a DDR memory controller varies depending on the board implementation, DDR devices, and internal factors on the memory controller. Implementations using a coarser granularity potentially  decrease the accuracy of delay provided by the delay circuit versus the required delay.

              The conventional memory controller circuit (see Figure 2) uses a delay-locked loop (DLL) to generate the required DQS delay. A master/slave scheme is typically implemented in which a master is calibrated to generate the control settings for the slave delay elements. This implementation uses the half-period of the system clock to calibrate the master delay element that then sets the slave delay elements.

              In systems where multiple delays are required, a multiplexer selects different taps (delay element outputs) of the slave as needed. Although the delay elements are analog and have fine granularity, the use of a multiplexer on delay taps results in coarse granularity of the overall delay. This coarseness often means the delay supplied by the delay circuit has a larger error. This delay error is unacceptable as memory technology advances.

              Another problem with this architec...