Browse Prior Art Database

SIMPLIFIED TRANSCEIVER FOR TDD SYSTEMS

IP.com Disclosure Number: IPCOM000008411D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-12
Document File: 3 page(s) / 131K

Publishing Venue

Motorola

Related People

Randall Hillock: AUTHOR

Abstract

In a time division duplex (TDD) system the radio transmits and receives on the same frequency. The transmission and reception are offset in time. Often the transmission slot and the reception slot are adjacent in time and only a small guard time separates them. In many applications this time is rless than 4 p. sec. To accommodate this require- ment a transceiver must be able to switch between eception and transmission and visa versa very quickly. A typical transceiver for the ISM band that satisfies this requirement is shown below in Figure 1, Fig. 1 The diagram in Figure 1 is a wireless data trans- ceiver intended the ISM band. Dual-conversion in the receiver is used in order to achieve 50 dB of selectivity at 4 MHz offset (I MHz channels). The signal used for transmission is generated by dividing the 650 MHz offset PLL by two and then mixing this 325 MHz signal with the 2075-2175 MHz PLL signal to form a 2400-2500 MHz signal. Reception is accomplished by mixing down the 2400-2500 MHz input signal with the 2075-2175 MHz PLL signal to form a 325 MHz first IF signal. Then, the 325 MHz IF signal is mixed down with the 314.3 MHz PLL to form a 10.7 MHz second IF signal. This 10.7 MHz signal is fed into a detector.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 3

MOTOROLA Technical Developments

SIMPLIFIED TRANSCEIVER FOR TDD SYSTEMS

by Randall Hillock

In a time division duplex (TDD) system the radio transmits and receives on the same frequency.

less than 4 p. sec. To accommodate this require- ment a transceiver must be able to switch between

The transmission and reception are offset in time.

Often the transmission slot and the reception slot

are adjacent in time and only a small guard time

separates them. In many applications this time is

reception and transmission and visa versa very

quickly. A typical transceiver for the ISM band that

satisfies this requirement is shown below in Figure 1,

Fig. 1

The diagram in Figure 1 is a wireless data trans-

ceiver intended the ISM band. Dual-conversion in the receiver is used in order to achieve 50 dB of selectivity at 4 MHz offset (I MHz channels). The signal used for transmission is generated by dividing the 650 MHz offset PLL by two and then mixing this 325 MHz signal with the 2075-2175 MHz PLL signal to form a 2400-2500 MHz signal. Reception is accomplished by mixing down the 2400-2500 MHz input signal with the 2075-2175 MHz PLL signal to form a 325 MHz first IF signal. Then, the 325 MHz IF signal is mixed down with the 314.3 MHz PLL to form a 10.7 MHz second IF

signal. This 10.7 MHz signal is fed into a detector.

The divide by two scheme with the 650 MHz PLL is employed so that energy from the offset PLL (self-quieter) does not couple into the 325 MHz IF during reception and degrade performance. Switching between reception and transmission is achieved by turning the divide by two block after the offset PLL on for transmission and off for recep- tion. All three loops are active during reception and transmission so the switch between reception and transmission could occur less than 4 p set because the response time of the divide by two is less than 1 p, sec.

1, Motorola. Inc. 1997

38 December 1997

[This page contains 15 pictures or other non-text objects]

Page 2 of 3

0 M

MOTOROLA Technical Developments

  The above has proven to work, however, as the To simplify the transceiver I propose to elimi- demand for smaller, less expensive, and more eff- nate one of the PLL's. A main PLL will be still cient radios become greater, the three PLL's with employed, however, the 2nd LO and Offset PLL divide by two scheme is no longer the most efficient signals will be derived from a single source. implementation. The need arises to simplify the Consider the block diagram in Figure 2,
above implementation.

I

Recovered Analog

Mod sens= 680 KHZ,"

Fig. 2

  The transceiver in Figure 2 consists of a main PLL at 2 1...