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Method for a linear voltage conversion below 100-nm with a pseudodiode driver operating in a region below threshold

IP.com Disclosure Number: IPCOM000008414D
Publication Date: 2002-Jun-12
Document File: 5 page(s) / 155K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a linear voltage conversion below 100-nm with a pseudodiode driver operating in a region below threshold. Benefits include improved functionality and improved performance.

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Method for a linear voltage conversion below 100-nm with a pseudodiode driver operating in a region below threshold

Disclosed is a method for a linear voltage conversion below 100-nm with a pseudodiode driver operating in a region below threshold. Benefits include improved functionality and improved performance.

Background

              Reducing the supply voltage, Vcc, is one of the most efficient conventional techniques for reducing the power consumption of CMOS circuits, particularly microprocessors. However, the signal propagation delay of circuits increases as the supply voltage decreases. Reasonable performance degradations in noncritical units may be tolerable. Any performance penalty in a critical path instantly degrades microprocessor performance. This situation suggests that utilizing more-than-one Vcc would be energy efficient. Higher supply voltage, VccH, would maintain the performance of critical units. A lower supply voltage, VccL, could be utilized on noncritical units to achieve considerable power savings without significantly degrading overall performance.

              One of the main issues in multi-Vcc chip design is the cost of additional power supplies. Off-chip power supplies are relatively expensive, consume a significant portion of the off-chip area, and result in major off-chip redesign. On-chip, compact, robust, efficient DC/DC converters reduce the cost for additional Vccs while enabling low power, high performance microprocessors.

              Conventional on-chip DC/DC conversion techniques (without inductive elements) can be divided into two main categories: linear converters, and switch-capacitance-based converters.

              The power-efficiency of linear down-converters is the ratio of the low voltage to the high voltage, VccL/VccH  (VccL is less than VccH). VccH is the input DC voltage. VccL is the output DC voltage of the converters. Larger VccL/VccH linear converters have high-power efficiency while occupying considerably less on-chip area.

              The output DC voltage is kept at a required (fixed) level by controlling the conductivity of the transistor Mp0 (MN0) relative to the output load (see Figure 2). Because the output load may change between its minimum and maximum levels, the conductivity of MP0 is continuously controlled. This result is achieved by comparing the output voltage level to a reference voltage level. The differential amplifier detects and amplifies the voltage difference. The output of the amplifier is fed back to the gate of the MP0 (MN0) to compensate the output error.

              Switching converters can provide good power efficiency over a large down-conversion range. However, the capacitances require a significantly large area of the chip.

              The entire system can be viewed as a regulator, with well-known problems such as stability issues, settling time, and output over/under-shoots. These factors set a number of severe contradictory requirements on the design and performance of the regulator system, including an accurate amplifier with an optimal gain....