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Method for a programmable fractional multiplier PLL clock generation

IP.com Disclosure Number: IPCOM000008415D
Publication Date: 2002-Jun-12
Document File: 3 page(s) / 96K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a programmable fractional multiplier phased-lock loop (PLL) clock generation. Benefits include improved performance.

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Method for a programmable fractional multiplier PLL clock generation

Disclosed is a method for a programmable fractional multiplier phased-lock loop (PLL) clock generation. Benefits include improved performance.

Background

              In a typical conventional PLL clocking system, a lower clock frequency is input to the PLL as the reference clock. A second input is applied after dividing the output clock (PLL output) by a ratio as a feedback clock. The PLL or clocking generator outputs a frequency that can be expressed as N * Fref, where N is an integer. In a clocking system with a fractional multiplier where N is not an integer, not all the edges are available to generate the required frequency. 

Description

              The disclosed method is a clock synthesizer with a fractional multiplier. The method can be implemented in several ways.

              One solution utilizes cascaded multiple PLLs (see Figure 1). The divide ratio used as an example is 18.75  but the same solutions can be adapted to other fractional ratios by using programmable dividers. This configuration requires bandwidth tracking that increases design complexity, a large area, and high-cost PLL analog power-supply filtering due to two PLLs.

              A single PLL solution requires the PLL to generate a very high frequency beyond the technology’s capability (see Figure 2). This solution is more noise sensitive and still requires expensive analog power-supply filtering due to the extreme high frequency. The divide by 4 can be at the front end but results i...