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Method for a Switch-on-Event Multithreading algorithm using micro-code emulation in Instruction Set Architecture with dual processors

IP.com Disclosure Number: IPCOM000008416D
Publication Date: 2002-Jun-12
Document File: 6 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a Switch-on-Event Multithreading (SoEMT) algorithm using micro-code emulation in Instruction Set Architecture (ISA) with dual processors. Benefits include improved performance.

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Method for a Switch-on-Event Multithreading algorithm using micro-code emulation in Instruction Set Architecture with dual processors

Disclosed is a method for a Switch-on-Event Multithreading (SoEMT) algorithm using micro-code emulation in Instruction Set Architecture (ISA) with dual processors. Benefits include improved performance.

Background

              Multithreading (MT) is a technique for improving microprocessor throughput with relatively little impact on die size. MT architecture enables multiple code streams to be executed simultaneously by sharing the resources of a single core pipeline. A processor that supports MT is viewed by the operating system as multiple logical processors. A Logical Processor is a logical set of physical resources that enables the physical processor to execute from different code streams.

              Several algorithms enable the sharing of resources among threads, such as switch-on-event and simultaneous multithreading. SoEMT enables multiple logical processors to share a single execution pipeline, but only one logical processor is active and can issue instructions into the core pipeline.

              Adding MT to an existing design requires some micro-architecture resources to be replicated. A decision must be made for each micro-architecture resource either to be shared among threads or to be replicated. On the other hand, architecture resources, such as general registers and instruction pointer, must be replicated due to the programming model, which treats each logical processor as an independent entity. Because the processor supports both element management (EM) and 32-bit instruction set execution, these resources must be replicated to enable the operating system (OS) to dispatch to the processor any mix of threads at the same time.

Description

              The disclosed method implements SoEMT in ISA with dual processors. The method reduces or eliminates, changes in the 32-bit side of the machine. This approach simplifies the design and reduces validation and design risk when adding MT support. This technique utilizes the existing 32-bit hardware to emulate SoEMT by existing micro-code that is conventionally used for switching between EM and 32-bit architecture (see Figure 2).

              A processor supports up to three threads of any mix of EM and 32-bit instruction streams. Only one thread is active at a time, and up to three threads can be executed at a time. However, the OS must view the processor as six logical processors, three EM logical processors and three 32-bit logical processors. This configuration enables the OS to d...