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Low Capacitance Bond Pad Structure for Low K Intermetal Dielectric Silicon Process

IP.com Disclosure Number: IPCOM000008418D
Publication Date: 2002-Jun-12
Document File: 2 page(s) / 77K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that consists of a bond pad structure used to conduct electrical signals on and off a silicon circuit via a wire bond. Benefits include less distortion of high frequency signals on and off the silicon circuit.

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Low Capacitance Bond Pad Structure for Low K Intermetal Dielectric Silicon Process

Disclosed is a method that consists of a bond pad structure used to conduct electrical signals on and off a silicon circuit via a wire bond. Benefits include less distortion of high frequency signals on and off the silicon circuit.

Background

Currently, a multi-layer metal structure, with low K dielectric insulating layers, is used to support the wire bond pad. This structure has a pad capacitance > 300 fF, which exceeds the target bond pad capacitance for 10 GHz circuits.

General Description

The bond pad structure conducts electrical signals on and off a silicon circuit via a wire bond. The structure is used to mechanically support the wire bonding and subsequent assembly operations. The structure works by reducing the capacitance of the bond pad so that high frequency signals (>= 10 GHz) can be conducted on and off the silicon circuit with less distortion (see Figure 1).

Advantages

The disclosed method offers inexpensive wirebond packaging for chips that require 10 GHz signaling, and causes less distortion during high frequency signals on and off the silicon circuit.

Disclosed anonymously