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Method for a multifunction, multiport bridgeless gigabit Ethernet concept

IP.com Disclosure Number: IPCOM000008439D
Publication Date: 2002-Jun-13
Document File: 4 page(s) / 195K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a multifunction, multiport bridgeless gigabit Ethernet concept. Benefits include improved performance.

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Method for a multifunction, multiport bridgeless gigabit Ethernet concept

Disclosed is a method for a multifunction, multiport bridgeless gigabit Ethernet concept. Benefits include improved performance.

Description

              The disclosed method is a multiport gigabit Ethernet controller implemented in a multifunction host environment. Key elements of the method include:

·        Integration of a number (designated as N) of LANs into one piece of silicon (N-way)

·        Shared host interface (such as PCI/PCI-X) for both LANs

·        Internal host arbitration mechanism

·        Shared manageability interface (such as SMBus) for each LAN

·        Shared local memory interface (such as Flash) for each LAN

·        Shared local configuration memory interface (such as EEPROM) for each LAN

Advantages

              The disclosed method provides advantages including:

·        Lower cost by optimizing silicon and pin count

·        Higher performance by using a single, high-speed host interface (bridge not needed) and avoiding bridge latency

·        Smaller motherboard surface area required

Detailed description

              The disclosed method describes a number (designated as n) of host cores and includes an arbitration mechanism to track a request queue for access. The method may be implemented as a variety of designs including a 4-way multifunction device (see Figure 1) or a dual-port dual-function PCI/PCI-X Gigabit controller (see Figure 2). The disclosed method includes two host cores with an internal arbiter between the two cores (see Figure 3).

              A single PCI/PCIX interfac...