Browse Prior Art Database

MAINTAINING STABLE PLL PARAMETERS

IP.com Disclosure Number: IPCOM000008445D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-14
Document File: 6 page(s) / 177K

Publishing Venue

Motorola

Related People

Neil Gutierrez: AUTHOR

Abstract

Maintaining stable Phase Lock Loop (PLL) parameters (e.g. jitter and peaking) is a key goal in PLL based clock driver designs. Unfortunately, in typical clock driver designs the PLL parameters become unstable when the bandwidth of the PLL, Kpll, nears either the zero or pole of the loop filter (~2 and ~3, respectively). This paper focuses on a method of keeping PLL parameters stable by using an electronically adjustable loop filter to optimize the distance between ~2, ~3, and Kpll. The theories and equations presented are referenced from the book by Dan Wolaver, "Phase-Locked Loop Circuit Design".

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 6

MOlOROLA Technical Developments

@

MAINTAINING STABLE PLL PARAMETERS

by Neil Gutierrez

1 .O INTRO/PROBLEM

  Maintaining stable Phase Lock Loop (PLL) parameters (e.g. jitter and peaking) is a key goal in PLL based clock driver designs. Unfortunately, in typical clock driver designs the PLL parameters become unstable when the bandwidth of the PLL, Kpll, nears either the zero or pole of the loop filter (~2 and ~3, respectively). This paper focuses on a method of keeping PLL parameters stable by using an electronically adjustable loop filter to optimize the distance between ~2, ~3, and Kpll. The theories and equations presented are referenced from the book by Dan Wolaver, "Phase-Locked Loop Circuit Design".

2.0 EQUATIONS

The following equations are used to describe the method of keeping stable PLL parameters.

w2 = I

Rf* Cf

w3 = I

where...

w2 and w3 are the zero and pole of the loop filter Rfis the resistance of the zero

Cfis the capacitance of the zero Ri is the resistance of the pole

Ci is the capacitance of the pole

Kpll is the bandwidth of the PLL

Kh is the loop filter gain

Ko is the voltage controlled oscillator gain

Kd is the phase detector gain N is the feedback division

3.0 SOLUTION

  The first step is to design the bandwidth of the PLL, Kpll, to be an ideal distance from the zero and pole of the loop filter with the lowest feedback division, N. This insures that the PLL parameters are stable at the lowest division. As N increases, Kpll moves toward w2 and away from w3 (see Figure I). Therefore, the stability of the PLL para- meters will be the ratio of Kpll to ~2.

Ri l Ci

(Equation 1)

(Equation 2)

(Equation 3)

(Equation 4)

Kpll =

Kh l Ku . Kd N

Kh =

If Motorola. 1°C. 19Y7 82 December I997

[This page contains 14 pictures or other non-text objects]

Page 2 of 6

Technical Developments

8 MO7-OROLA

\

- Frequency

4 IdealDistance 0

X-,

            I w2 - Kpll withhigher N

Kh.- _ - _ - _

Fig. 1 Movement of Kpll toward w2 at higher

  However, if w2 moves as Kpll moves such that the distance X is kept constant, then the PLL parameters will remain stable. This movement of w2 and Kpll can be accomplished by changing Rf as N increases (see EQ I, EQ 3, and EQ 4). How much should Rf change? The goal is to keep X constant throughout the range of N.

Using EQ I- EQ 4: (Equation 5)

gain (Kd), and the passive components Ri and Cf are constant.

For example if N = 4 to 16, Ideal Distance X = 4, and Constant = 1, then at the lowest division:

N=4 Rf,=fl4=4 (Equation 6)

At higher divisions Rf must change by:

X-w2 = Kpll

Ri

N=6 Rf =fi = (l.22xRf,) N=16 Rf=m=@xRf,)

Rf = X*N*

(Equation 7)

  There is a limit to how far Rf can increase. As Rf increases, so does the loop tilter gain, Kh (EQ 4). Care must be taken to keep Kh below OdB to avoid instability (see Figure 2).

  EQ 5 shows that in order to keep the distance, X, between K...