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A METHOD FOR SIMULTANEOUS RETENTION AND IDDQ TESTING OF EMBEDDED MEMORIES AND SCAN SEQUENTIAL LOGIC

IP.com Disclosure Number: IPCOM000008450D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-14
Document File: 5 page(s) / 285K

Publishing Venue

Motorola

Related People

Matthew Pressly: AUTHOR [+2]

Abstract

Microprocessors commonly contain embedded arrays of memory cells (called memories for the duration of this paper) for caching of instructions or data or for direct use by the customer. They also contain large numbers of individual storage cells, implemented as flip-flops' or latches. These are used throughout the microprocessor for storage of state for state machines, for data and address regis- ters, and for many other uses. The M68060 micro- processor, for example, contains about thirteen thousand flip-flops and 16Kb of cache memory.

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M-LA Technical Developments

A METHOD FOR SIMULTANEOUS RETENTION AND IDDQ TESTING OF EMBEDDED MEMORIES AND SCAN SEQUENTIAL LOGIC

by Matthew Pressly and Alfred Crouch

INTRODUCTION

  Microprocessors commonly contain embedded arrays of memory cells (called memories for the duration of this paper) for caching of instructions or data or for direct use by the customer. They also contain large numbers of individual storage cells, implemented as flip-flops' or latches. These are used throughout the microprocessor for storage of state for state machines, for data and address regis- ters, and for many other uses. The M68060 micro- processor, for example, contains about thirteen thousand flip-flops and 16Kb of cache memory.

  Microprocessors are commonly used in applica- tions where reads and writes of memory cells and flip-flops happen infrequently. This is especially true in embedded and low power applications, where the microprocessor may be placed in a low- power mode of operation in which calculations within it cease for a time span of anywhere from several seconds to hours or days. Since there exist manufacturing defects that can cause data values stored in memory cells or flip-flops to decay to the point that the stored data changes state (i.e. a stored logic-l erroneously becomes a logic-o, or vice versa), it is critical to perform data retention tests on each microprocessor. A data retention test causes known logic values to be stored in the memory cells, then it pauses for a (relatively) long period of time (lOO-500ms, typically) to allow for the possi- bility of data value decay in defective products, then reads the stored values and compares them to the previously written values. Any discrepanc$ causes the microprocessor to fail the test. The test sequence is repeated for complementary data values and is also repeated for flip-flops, resulting in multiple pauses, which dominate the time spent in data retention tests.

The total time spent in pauses in data retention tests is often twenty-five to fifty percent of the total

test time for a microprocessor, which is a significant cost, This paper discusses a method whereby the number of pauses required to test a microprocessor for data retention can be reduced to a minimum, thus significantly reducing the cost of testing micro- processors that contain embedded memories.

PRIOR ART

  The prior art for this invention consists of two classes of microprocessors-those that provide a direct means of controlling and observing data values in flip-flops through addition of scan test logic, and those that do not. Scan is a method whereby the flip-flops are interconnected into one or more scan chains. Through serial operation of scan chains, known data can be shifted into every scanned flip-flop, thus controlling its state. Data that is resident in the flip-flops can also be unloaded and observed by serially shifting the data onto one or more output pins. There exist full scan micro- processors, in whic...