Browse Prior Art Database

METHOD OF ELECTROCHEMICALLY ETCHING DIAPHRAGM FOR CMOS INTEGRATED PRESSURE SENSOR

IP.com Disclosure Number: IPCOM000008452D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-14
Document File: 3 page(s) / 116K

Publishing Venue

Motorola

Related People

K. Sooriakumar: AUTHOR [+3]

Abstract

Making a thin diaphragm in silicon wafers for and electrochemical etch stop (ECE). sensing applications is a critical process in sensor fabrication. For pressure sensors, deep cavities are Among these etch stop technologies, the elec- etched in the back of silicon wafers to make thin trochemical etch stop offers many advantages. ECE diaphragms (see Figure 1). Many etch stop technolo- can be used in conjunction with Bipolar as well as gies are used in forming the diaphragm (see Figure 2). CMOS integrated circuits.

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MOTOROLA Technical Developments

METHOD OF ELECTROCHEMICALLY ETCHING DIAPHRAGM FOR CMOS INTEGRATED PRESSURE SENSOR

by K. Sooriakumar, Bob Tucker and Cindy Ray

  Making a thin diaphragm in silicon wafers for and electrochemical etch stop (ECE). sensing applications is a critical process in sensor
fabrication. For pressure sensors, deep cavities are Among these etch stop technologies, the elec- etched in the back of silicon wafers to make thin trochemical etch stop offers many advantages. ECE diaphragms (see Figure 1). Many etch stop technolo- can be used in conjunction with Bipolar as well as gies are used in forming the diaphragm (see Figure 2). CMOS integrated circuits.

These are timed etch, P++etch stop, oxide etch stop,

Fig. 1 Cross section of pressure sensor

n - epi

(a) Timed etch (b) P++ ,etch stop

n - wafer n - eDi

(c) Bonded wafer oxide/no oxide

(d) ECE etch stop

Fig. 2 Etch stop technologies

0 Mcmrola, Inc. ,997 79 December 1997

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MOTOROLA Technical Developments

  For CMOS integrated pressure sensors, the p-type piezoresistive coefficient is much higher implementation of electrochemical etch stop (ECE) than n-type. In this process, n-well is used to fabri- presents many challenges. Since the biasing for cate p-resistor. Forming a diaphragm in conjunction ECE requires n or p- substrate, the substrate with CMOS process requires an additional n layer for CMOS process need to be modified. The CMOS impeded in the substrate. In doing so, a thin layer is fabricated in p substrate. Fabrication of piezo- of epi or diffused material is grown on p substrate resistor also requires n well or substrate since followed by epitaxial growth (see Figure 3).

Fig. 3 Substrate for ECE-CMOS

  Wafers processed by the ECE technique consist of a p-type substrate with an n-type epitaxial (or diffused) layer, as illustrated in Figure 4. The back side of the wafer is patterned with masking layer(s) to produce a matrix of rectangular (or any shape) openings which defines the areas of silicon that will be etched by the KOH solution, Electrical contact to a network of metal current-carrying grids on the wafer front conveys an externally generate...