Browse Prior Art Database

Method for backside infrared emission static logic state mapping

IP.com Disclosure Number: IPCOM000008468D
Publication Date: 2002-Jun-17
Document File: 4 page(s) / 176K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for backside infrared emission static logic state mapping. Benefits include improved performance and improved productivity in performing silicon debug and fault isolation on backside integrated circuits.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 49% of the total text.

Method for backside infrared emission static logic state mapping

Disclosed is a method for backside infrared emission static logic state mapping. Benefits include improved performance and improved productivity in performing silicon debug and fault isolation on backside integrated circuits.

Background

              The conventional methods used for silicon debug and fault isolation on logic circuits typically involve laser voltage probing (LVP) and probeless debug/fault isolation (FI) techniques. LVP is subject to limitations, including:

·        Capability to probe only a single point at a time

·        Requirement for looping the pattern with a maximum and minimum loop length

·        Typically long through-put times (hours to days) for acquiring accurate waveforms

              Similarly, probeless approaches require long times to perform the following tasks to determine the point of failure:

·        Run simulations

·        Capture data through:
              -             Scan out
              -             Array dump
              -             Tracing schematics

              The probeless approaches are limited as only certain signals can be accessed using the design-for-testability (DFT) features. Obtaining access to other signals often requires complex microcode patches. To be effective at probeless debug and FI, extensive architecture and circuit knowledge is required on the part of the engineer doing the debug/FI.

              Conventionally, emission microscopy has mainly been used to detect gross defects and leakage that caused backside emission.

General description

              The disclosed method uses backside infrared emission static logic state mapping. The logic states of an integrated circuit are determined by using an infrared emission microscope (IREM) to observe the backside infrared emissions and to correlate the observed emissions to logic states.

              Unlike LVP, the IREM captures the emission from an entire area, probing many devices simultaneously. No looping is required, enabling functional patterns of any size to be used and probing to occur at any point within the pattern. The acquisition time of IREM is also much less than LVP. The entire acquisition time, including setup for IREM, is approximately 30 minutes with subsequent data taking only minutes to acquire. Because the entire backside is observable by the IREM, this method can be applied to any circuit that has sufficient observable emission. That is, the devices must be large enough to produce an observable amount of leakage current.

              With the disclosed method, the engineer performing the analysis does not need extensive product architecture or circuit knowledge. The only requirement is to know how to correlate the emissions to the circuit by using established emission-to-logic state mapping models.

Advantages

              Technical disclosed method provides advantages over current methods, including:

·        Less-complex procedures

·        Fast data-acquisition times

·        Faster through-put times on debug and FI cases

Detail description

              The disclosed method is most likely to be used in conjunction with the LVP and probeless approaches to give faster throughput-tim...