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Successive Approximation Frequency Lock Loop Utilizing a Digital Controlled Oscillator

IP.com Disclosure Number: IPCOM000008508D
Publication Date: 2002-Jun-18
Document File: 3 page(s) / 122K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention arises from the need to synchronize a local oscillator at +/- Pi precision to a master clock at frequency Fm within +/- Pf precision within a short period of time Ts. This is necessary to establish communication on a network without the use of a high precision local oscillator. Oscillator synchronization is necessary in communication networks where high precision oscillators are not used. A section of the header of an incoming message consists of alternating high and low states. This section is referred to as the 'synch field.' The local oscillator has the duration of this 'synch field' to synchronize with the data rate of the incoming message to enable proper reception of the incoming message. There are close technologies that potentially could meet these requirements, but with disadvantages. Typically, this requirement would be met with a Phase Lock Loop (PLL). However, because of the short time Ts in which to acquire lock, the gain required would be large, resulting in poor stability of the PLL. Another method includes measuring the time between the falling edges of both the start bit and bit Fm*Ts, and then dividing the obtained value by Fm*Ts. This approach is complex, and requires an oscillator with a base frequency of Fm/Pf, a log2 (Fm*Ts) bit counter, a log2 (Fm*Ts/Pf) bit counter, a log2 (1/Pf) data latch and a log2 (1/Pf) bit comparator. Therefor, there is a need for a method and circuit for synchronizing a local oscillator with precision to a master clock within a short period of time using successive approximation frequency lock loop utilizing a digital controlled oscillator.

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Successive Approximation Frequency Lock Loop Utilizing a Digital Controlled Oscillator

         This invention arises from the need to synchronize a local oscillator at +/- Pi precision to a master clock at frequency Fm within +/- Pf precision within a short period of time Ts.  This is necessary to establish communication on a network without the use of a high precision local oscillator.  Oscillator synchronization is necessary in communication networks where high precision oscillators are not used.  A section of the header of an incoming message consists of alternating high and low states.  This section is referred to as the ‘synch field.’  The local oscillator has the duration of this ‘synch field’ to synchronize with the data rate of the incoming message to enable proper reception of the incoming message.  There are close technologies that potentially could meet these requirements, but with disadvantages.  Typically, this requirement would be met with a Phase Lock Loop (PLL).  However, because of the short time Ts in which to acquire lock, the gain required would be large, resulting in poor stability of the PLL.  Another method includes measuring the time between the falling edges of both the start bit and bit Fm*Ts, and then dividing the obtained value by Fm*Ts. This approach is complex, and requires an oscillator with a base frequency of Fm/Pf, a log2 (Fm*Ts) bit counter, a log2 (Fm*Ts/Pf) bit counter, a log2 (1/Pf) data latch and a log2 (1/Pf) bit comparator.

Therefor, there is a need for a method and circuit for synchronizing a local oscillator with precision to a master clock within a short period of time using successi...