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VOLTAGE DOUBLER WITH RISE AND FALL TIME ATTENTUATOR

IP.com Disclosure Number: IPCOM000008516D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-19
Document File: 3 page(s) / 115K

Publishing Venue

Motorola

Related People

Wai-Hung Tsui: AUTHOR [+2]

Abstract

In today's paging application, the components within a paging system may include a receiver, a microcontroller, a voltage management IC, and others. A receiver plays an important role in receiving a page without errors. Unfortunately, most of the companion ICs within the pager could possibly gen- erate undesired harmonics that affect the accuracy of the receiver. In that situation, the outputs of these periodic output signals are desired to have slower rise and fall times. The rise and fall time attenuator illustrated in this paper serves a mean to effectively slow down the rise and fall times. In addition, it also reduces the trade off of power efficiency.

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MOTOROLA Technical Developments

VOLTAGE DOUBLER WITH RISE AND FALL TIME ATTENTUATOR

by Wai-Hung Tsui and Don Zobel

ABSTRACT

  In today's paging application, the components within a paging system may include a receiver, a microcontroller, a voltage management IC, and others. A receiver plays an important role in receiving a page without errors. Unfortunately, most of the companion ICs within the pager could possibly gen- erate undesired harmonics that affect the accuracy of the receiver. In that situation, the outputs of these periodic output signals are desired to have slower rise and fall times. The rise and fall time attenuator illustrated in this paper serves a mean to effectively slow down the rise and fall times. In addition, it also reduces the trade off of power efficiency.

PROBLEM

  A concern with the voltage doubler output would be the rise and fall times of the signal on the pump capacitor(Cp). If the fast rise and fall times

are too fast, the periodic signals on the top and bottom plates of the pump capacitor include harmonics that are in the same receiving frequency as the receiver and this could potentially cause some desense problems.

SOLUTION

  To prevent the desense problem from occurring, the rise and fall times of these signals must be slowed down. Referring to Figure 1, two feedback capacitors are used to slow down the rise and fall times. Each feedback capacitor is connected to a resistor and has a path either to VDDI or to ground.

In the charging phase, when PlCLK rises to a volt- age that is just enough to turn on the NMOS device(MNl) creating a current path between P2CA to ground. Suppose a fall time of tf is desired, P2CA is therefore defined to drop from 0.9*VDDl to 0.1 *VDD 1 within the time tf.

'> MOtorOla. 1°C. ,997

189 December 1997

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MOTOROLA Technical Developments

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